Gopher2600/hardware/cpu/definitions.csv

1	# instructions are defined with the following fields:
2	#
3	# opcode, mnemonic, cycles, addressing mode, page sensitivity, [effect category]
4	#
5	#
6	# effect category can be one of three types (READ is the default if no effect category is given)
7	#
8	# 1. READ (instruction only reads from memory - or not at all in the case of IMPLIED instructions
9	# 2. WRITE (instruction changes memory)
10	# 3. RMW (instruction reads, modifies and writes to memory)
11	# 4. FLOW (instruction explicitely affects the program counter)
12	# 5. SUB-ROUTINE (like FLOW but also writes to the stack)
13	#
14	# in the 6502 all instructions are considered to read from memory, even register only
15	# instructions (the IMPLIED addressing mode). in the hardware, this meant that the chip could forego
16	# on manufacturing costs.
17	#
18	# only some instructions however, ever *write* to memory. in the 6502 this is accomplished with a
19	# as well as read. in our emulation, we mark the instructions that write to memory by specifying
20	# the WRITE effect category
21	#
22	# a small class of instructions read AND write to memory (using the same address), these
23	# are the RMW class of instructions.
24	#
25	#
26	# note that the addressing mode /implies/ the number of bytes each instruction requires:
27	# (including the 1 byte required for the opcode)
28	#
29	# IMPLIED = 1
30	# IMMEDIATE = 2
31	# ZERO PAGE = 2
32	# all others = 3
33	#
34	# TODO: maybe the number of cycles can be inferred in a similar way
35	# no operation
36	0xea, NOP, 2, IMPLIED, False
37	0x04, NOP, 3, ZERO_PAGE, False
38	# status flags
39	0x58, CLI, 2, IMPLIED, False
40	0x78, SEI, 2, IMPLIED, False
41	0x18, CLC, 2, IMPLIED, False
42	0x38, SEC, 2, IMPLIED, False
43	0xd8, CLD, 2, IMPLIED, False
44	0xf8, SED, 2, IMPLIED, False
45	0xb8, CLV, 2, IMPLIED, False
46	# stack
47	0x48, PHA, 2, IMPLIED, False, WRITE
48	0x68, PLA, 3, IMPLIED, False
49	0x08, PHP, 2, IMPLIED, False, WRITE
50	0x28, PLP, 3, IMPLIED, False
51	# register transfer
52	0x8a, TXA, 2, IMPLIED, False
53	0xaa, TAX, 2, IMPLIED, False
54	0xa8, TAY, 2, IMPLIED, False
55	0x98, TYA, 2, IMPLIED, False
56	0xba, TSX, 2, IMPLIED, False
57	0x9a, TXS, 2, IMPLIED, False
58	# bitwise operations
59	0x49, EOR, 2, IMMEDIATE, False
60	0x45, EOR, 3, ZERO_PAGE, False
61	0x55, EOR, 4, INDEXED_ZERO_PAGE_X, False
62	0x4d, EOR, 4, ABSOLUTE, False
63	0x5d, EOR, 4, ABSOLUTE_INDEXED_X, True
64	0x59, EOR, 4, ABSOLUTE_INDEXED_Y, True
65	0x41, EOR, 6, PRE_INDEX_INDIRECT, False
66	0x51, EOR, 5, POST_INDEX_INDIRECT, True
67	0x09, ORA, 2, IMMEDIATE, False
68	0x05, ORA, 3, ZERO_PAGE, False
69	0x15, ORA, 4, INDEXED_ZERO_PAGE_X, False
70	0x0d, ORA, 4, ABSOLUTE, False
71	0x1d, ORA, 4, ABSOLUTE_INDEXED_X, True
72	0x10, ORA, 4, ABSOLUTE_INDEXED_Y, True
73	0x01, ORA, 6, PRE_INDEX_INDIRECT, False
74	0x11, ORA, 5, POST_INDEX_INDIRECT, True
75	0x29, AND, 2, IMMEDIATE, False
76	0x25, AND, 3, ZERO_PAGE, False
77	0x35, AND, 4, INDEXED_ZERO_PAGE_X, False
78	0x2d, AND, 4, ABSOLUTE, False
79	0x3d, AND, 4, ABSOLUTE_INDEXED_X, True
80	0x39, AND, 4, ABSOLUTE_INDEXED_Y, True
81	0x21, AND, 6, PRE_INDEX_INDIRECT, False
82	0x31, AND, 5, POST_INDEX_INDIRECT, True
83	# load register
84	0xa9, LDA, 2, IMMEDIATE, False
85	0xa5, LDA, 3, ZERO_PAGE, False
86	0xb5, LDA, 4, INDEXED_ZERO_PAGE_X, False
87	0xad, LDA, 4, ABSOLUTE, False
88	0xbd, LDA, 4, ABSOLUTE_INDEXED_X, True
89	0xb9, LDA, 4, ABSOLUTE_INDEXED_Y, True
90	0xa1, LDA, 6, PRE_INDEX_INDIRECT, False
91	0xb1, LDA, 5, POST_INDEX_INDIRECT, True
92	0xa2, LDX, 2, IMMEDIATE, False
93	0xa6, LDX, 3, ZERO_PAGE, False
94	0xb6, LDX, 4, INDEXED_ZERO_PAGE_Y, False
95	0xae, LDX, 4, ABSOLUTE, False
96	0xbe, LDX, 4, ABSOLUTE_INDEXED_Y, True
97	0xa0, LDY, 2, IMMEDIATE, False
98	0xa4, LDY, 3, ZERO_PAGE, False
99	0xb4, LDY, 4, INDEXED_ZERO_PAGE_X, False
100	0xac, LDY, 4, ABSOLUTE, False
101	0xbc, LDY, 4, ABSOLUTE_INDEXED_X, True
102	# register operations
103	0xe8, INX, 2, IMPLIED, False
104	0xc8, INY, 2, IMPLIED, False
105	0xca, DEX, 2, IMPLIED, False
106	0x88, DEY, 2, IMPLIED, False
107	0x0a, ASL, 2, IMPLIED, False
108	0x06, ASL, 5, ZERO_PAGE, False
109	0x16, ASL, 6, INDEXED_ZERO_PAGE_X, False
110	0x0e, ASL, 6, ABSOLUTE, False
111	0x1e, ASL, 7, ABSOLUTE_INDEXED_X, False
112	0x4a, LSR, 2, IMPLIED, False
113	0x46, LSR, 5, ZERO_PAGE, False
114	0x56, LSR, 6, INDEXED_ZERO_PAGE_X, False
115	0x4e, LSR, 6, ABSOLUTE, False
116	0x5e, LSR, 7, ABSOLUTE_INDEXED_X, False
117	0x69, ADC, 2, IMMEDIATE, False
118	0x65, ADC, 3, ZERO_PAGE, False
119	0x75, ADC, 4, INDEXED_ZERO_PAGE_X, False
120	0x6d, ADC, 4, ABSOLUTE, False
121	0x7d, ADC, 4, ABSOLUTE_INDEXED_X, True
122	0x79, ADC, 4, ABSOLUTE_INDEXED_Y, True
123	0x61, ADC, 6, PRE_INDEX_INDIRECT, False
124	0x71, ADC, 5, POST_INDEX_INDIRECT, True
125	0xe9, SBC, 2, IMMEDIATE, False
126	0xe5, SBC, 3, ZERO_PAGE, False
127	0xf5, SBC, 4, INDEXED_ZERO_PAGE_X, False
128	0xed, SBC, 4, ABSOLUTE, False
129	0xfd, SBC, 4, ABSOLUTE_INDEXED_X, True
130	0xf9, SBC, 4, ABSOLUTE_INDEXED_Y, True
131	0xe1, SBC, 6, PRE_INDEX_INDIRECT, False
132	0xf1, SBC, 5, POST_INDEX_INDIRECT, True
133	0x6a, ROR, 2, IMPLIED, False
134	0x66, ROR, 5, ZERO_PAGE, False
135	0x76, ROR, 6, INDEXED_ZERO_PAGE_X, False
136	0x6e, ROR, 6, ABSOLUTE, False
137	0x7e, ROR, 7, ABSOLUTE_INDEXED_X, False
138	0x2a, ROL, 2, IMPLIED, False
139	0x26, ROL, 5, ZERO_PAGE, False
140	0x36, ROL, 6, INDEXED_ZERO_PAGE_X, False
141	0x2e, ROL, 6, ABSOLUTE, False
142	0x3e, ROL, 7, ABSOLUTE_INDEXED_X, False
143	# compare instructions
144	0xc9, CMP, 3, IMMEDIATE, False
145	0xc5, CMP, 3, ZERO_PAGE, False
146	0xd5, CMP, 4, INDEXED_ZERO_PAGE_X, False
147	0xcd, CMP, 4, ABSOLUTE, False
148	0xdd, CMP, 4, ABSOLUTE_INDEXED_X, True
149	0xd9, CMP, 4, ABSOLUTE_INDEXED_Y, True
150	0xc1, CMP, 6, PRE_INDEX_INDIRECT, False
151	0xd1, CMP, 5, POST_INDEX_INDIRECT, True
152	0xe0, CPX, 2, IMMEDIATE, False
153	0xe4, CPX, 3, ZERO_PAGE, False
154	0xec, CPX, 4, ABSOLUTE, False
155	0xc0, CPY, 2, IMMEDIATE, False
156	0xc4, CPY, 3, ZERO_PAGE, False
157	0xcc, CPY, 4, ABSOLUTE, False
158	0x24, BIT, 3, ZERO_PAGE, False
159	0x2c, BIT, 4, ABSOLUTE, False
160	# store register
161	0x85, STA, 3, ZERO_PAGE, False, WRITE
162	0x95, STA, 4, INDEXED_ZERO_PAGE_X, False, WRITE
163	0x8d, STA, 4, ABSOLUTE, False, WRITE
164	0x9d, STA, 5, ABSOLUTE_INDEXED_X, False, WRITE
165	0x99, STA, 5, ABSOLUTE_INDEXED_Y, False, WRITE
166	0x81, STA, 6, PRE_INDEX_INDIRECT, False, WRITE
167	0x91, STA, 6, POST_INDEX_INDIRECT, False, WRITE
168	0x86, STX, 3, ZERO_PAGE, False, WRITE
169	0x96, STX, 4, INDEXED_ZERO_PAGE_Y, False, WRITE
170	0x8e, STX, 4, ABSOLUTE, False, WRITE
171	0x84, STY, 3, ZERO_PAGE, False, WRITE
172	0x94, STY, 4, INDEXED_ZERO_PAGE_X, False, WRITE
173	0x8c, STY, 4, ABSOLUTE, False, WRITE
174	# memory instructions
175	0xe6, INC, 5, ZERO_PAGE, False, RMW
176	0xf6, INC, 6, INDEXED_ZERO_PAGE_X, False, RMW
177	0xee, INC, 6, ABSOLUTE, False, RMW
178	0xfe, INC, 7, ABSOLUTE_INDEXED_X, False, RMW
179	0xc6, DEC, 5, ZERO_PAGE, False, RMW
180	0xd6, DEC, 6, INDEXED_ZERO_PAGE_X, False, RMW
181	0xce, DEC, 6, ABSOLUTE, False, RMW
182	0xde, DEC, 7, ABSOLUTE_INDEXED_X, False, RMW
183	# flow control
184	0x4c, JMP, 3, ABSOLUTE, False, FLOW
185	0x6c, JMP, 5, INDIRECT, False, FLOW
186	# flow control (branch instructions) -- machine cycles count column is the fail count
187	# ie. when the branch condition isfalse and the PC allowed to advance as normal. if the
188	# branch succeeds then the PC is adjusted, taking an additional cycle.
189	0x90, BCC, 2, RELATIVE, False, FLOW
190	0xb0, BCS, 2, RELATIVE, False, FLOW
191	0xf0, BEQ, 2, RELATIVE, False, FLOW
192	0x30, BMI, 2, RELATIVE, False, FLOW
193	0xd0, BNE, 2, RELATIVE, False, FLOW
194	0x10, BPL, 2, RELATIVE, False, FLOW
195	0x50, BVC, 2, RELATIVE, False, FLOW
196	0x70, BVS, 2, RELATIVE, False, FLOW
197	0x20, JSR, 2, ABSOLUTE, False, SUB-ROUTINE
198	0x60, RTS, 3, IMPLIED, False, SUB-ROUTINE
199	# interrupts
200	0x00, BRK, 7, IMPLIED, False, WRITE
201	0x40, RTI, 6, IMPLIED, False