mirror of
https://github.com/Marat-Tanalin/bsnes-mt.git
synced 2024-05-28 17:17:20 -04:00
107 lines
3.3 KiB
C++
107 lines
3.3 KiB
C++
auto HG51B::readRegister(uint7 address) -> uint24 {
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switch(address) {
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case 0x01: return r.mul >> 24 & 0xffffff;
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case 0x02: return r.mul >> 0 & 0xffffff;
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case 0x03: return r.mdr;
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case 0x08: return r.rom;
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case 0x0c: return r.ram;
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case 0x13: return r.mar;
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case 0x1c: return r.dpr;
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case 0x20: return r.pc;
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case 0x28: return r.p;
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case 0x2e:
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io.bus.enable = 1;
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io.bus.reading = 1;
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io.bus.pending = 1 + io.wait.rom;
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io.bus.address = r.mar;
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return 0x000000;
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case 0x2f:
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io.bus.enable = 1;
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io.bus.reading = 1;
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io.bus.pending = 1 + io.wait.ram;
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io.bus.address = r.mar;
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return 0x000000;
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//constant registers
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case 0x50: return 0x000000;
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case 0x51: return 0xffffff;
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case 0x52: return 0x00ff00;
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case 0x53: return 0xff0000;
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case 0x54: return 0x00ffff;
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case 0x55: return 0xffff00;
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case 0x56: return 0x800000;
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case 0x57: return 0x7fffff;
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case 0x58: return 0x008000;
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case 0x59: return 0x007fff;
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case 0x5a: return 0xff7fff;
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case 0x5b: return 0xffff7f;
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case 0x5c: return 0x010000;
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case 0x5d: return 0xfeffff;
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case 0x5e: return 0x000100;
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case 0x5f: return 0x00feff;
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//general purpose registers
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case 0x60: case 0x70: return r.gpr[ 0];
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case 0x61: case 0x71: return r.gpr[ 1];
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case 0x62: case 0x72: return r.gpr[ 2];
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case 0x63: case 0x73: return r.gpr[ 3];
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case 0x64: case 0x74: return r.gpr[ 4];
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case 0x65: case 0x75: return r.gpr[ 5];
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case 0x66: case 0x76: return r.gpr[ 6];
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case 0x67: case 0x77: return r.gpr[ 7];
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case 0x68: case 0x78: return r.gpr[ 8];
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case 0x69: case 0x79: return r.gpr[ 9];
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case 0x6a: case 0x7a: return r.gpr[10];
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case 0x6b: case 0x7b: return r.gpr[11];
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case 0x6c: case 0x7c: return r.gpr[12];
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case 0x6d: case 0x7d: return r.gpr[13];
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case 0x6e: case 0x7e: return r.gpr[14];
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case 0x6f: case 0x7f: return r.gpr[15];
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}
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return 0x000000; //verified
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}
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auto HG51B::writeRegister(uint7 address, uint24 data) -> void {
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switch(address) {
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case 0x01: r.mul = r.mul & 0xffffffull | data << 24; return;
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case 0x02: r.mul = r.mul & ~0xffffffull | data << 0; return;
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case 0x03: r.mdr = data; return;
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case 0x08: r.rom = data; return;
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case 0x0c: r.ram = data; return;
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case 0x13: r.mar = data; return;
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case 0x1c: r.dpr = data; return;
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case 0x20: r.pc = data; return;
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case 0x28: r.p = data; return;
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case 0x2e:
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io.bus.enable = 1;
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io.bus.writing = 1;
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io.bus.pending = 1 + io.wait.rom;
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io.bus.address = r.mar;
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return;
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case 0x2f:
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io.bus.enable = 1;
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io.bus.writing = 1;
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io.bus.pending = 1 + io.wait.ram;
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io.bus.address = r.mar;
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return;
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case 0x60: case 0x70: r.gpr[ 0] = data; return;
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case 0x61: case 0x71: r.gpr[ 1] = data; return;
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case 0x62: case 0x72: r.gpr[ 2] = data; return;
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case 0x63: case 0x73: r.gpr[ 3] = data; return;
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case 0x64: case 0x74: r.gpr[ 4] = data; return;
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case 0x65: case 0x75: r.gpr[ 5] = data; return;
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case 0x66: case 0x76: r.gpr[ 6] = data; return;
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case 0x67: case 0x77: r.gpr[ 7] = data; return;
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case 0x68: case 0x78: r.gpr[ 8] = data; return;
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case 0x69: case 0x79: r.gpr[ 9] = data; return;
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case 0x6a: case 0x7a: r.gpr[10] = data; return;
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case 0x6b: case 0x7b: r.gpr[11] = data; return;
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case 0x6c: case 0x7c: r.gpr[12] = data; return;
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case 0x6d: case 0x7d: r.gpr[13] = data; return;
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case 0x6e: case 0x7e: r.gpr[14] = data; return;
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case 0x6f: case 0x7f: r.gpr[15] = data; return;
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}
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}
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