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Fix interrupt spelling.

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s/interupt/interrupt/
This commit is contained in:
Bobby Smiles 2017-03-07 06:17:04 +01:00
parent 2c12b82148
commit efdeaf32c7
31 changed files with 137 additions and 137 deletions
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4
RELEASE
View file

@ -363,7 +363,7 @@ what's new in 0.5:
feature. Mariokart's monitor in first race running fullspeed and
puzzle effect in banjo's intro are two examples that i can think
about but there are many more.
+ detection of VI interupt rate works on weird country codes
+ detection of VI interrupt rate works on weird country codes
+ better detection of self modifying code in dma
+ warnings fixed on new gcc versions
+ rsp's dmem and imem are now contiguous in PC's memory (some windows
@ -510,7 +510,7 @@ what's new in 0.1:
- Core
+ sram bug zelda oot fixed
+ flashram is working
+ a new interupt system that'll enabled
+ a new interrupt system that'll enabled
more accurate timing in the future but can cause
some compatibility issues right now
+ bug in DMULT/DMULTU opcode fixed

2
doc/new_dynarec.mediawiki
View file

@ -186,7 +186,7 @@ As in the original mupen64plus, the emulated clock runs at 37.5 MHz, and each in
==Interrupt handler==
When the cycle count register reaches its limit, cc_interrupt is called, which in turn calls gen_interupt [sic]. If interrupts are not enabled, cc_interrupt returns. If interrupts are enabled, and an interrupt is to be taken, the pending_exception flag will be set. In this case, cc_interrupt does not return, and instead pops the stack and causes an unconditional jump to the address in pcaddr (usually 0x80000180).
When the cycle count register reaches its limit, cc_interrupt is called, which in turn calls gen_interrupt. If interrupts are not enabled, cc_interrupt returns. If interrupts are enabled, and an interrupt is to be taken, the pending_exception flag will be set. In this case, cc_interrupt does not return, and instead pops the stack and causes an unconditional jump to the address in pcaddr (usually 0x80000180).
There is one additional case where the interrupt handler may be called. If interrupts were disabled, and are enabled by writing to coprocessor 0 register 12, any pending interrupts are handled immediately.

4
projects/VisualStudio2013/mupen64plus-core.vcxproj
View file

@ -124,7 +124,7 @@
</ClCompile>
<ClCompile Include="..\..\src\device\r4300\exception.c" />
<ClCompile Include="..\..\src\device\r4300\instr_counters.c" />
<ClCompile Include="..\..\src\device\r4300\interupt.c" />
<ClCompile Include="..\..\src\device\r4300\interrupt.c" />
<ClCompile Include="..\..\src\device\r4300\mi_controller.c" />
<ClCompile Include="..\..\src\device\r4300\new_dynarec\arm\arm_cpu_features.c">
<ExcludedFromBuild Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">true</ExcludedFromBuild>
@ -517,7 +517,7 @@
<ClInclude Include="..\..\src\device\r4300\exception.h" />
<ClInclude Include="..\..\src\device\r4300\fpu.h" />
<ClInclude Include="..\..\src\device\r4300\instr_counters.h" />
<ClInclude Include="..\..\src\device\r4300\interupt.h" />
<ClInclude Include="..\..\src\device\r4300\interrupt.h" />
<ClInclude Include="..\..\src\device\r4300\macros.h" />
<ClInclude Include="..\..\src\device\r4300\mi_controller.h" />
<ClInclude Include="..\..\src\device\r4300\new_dynarec\arm\arm_cpu_features.h">

6
projects/VisualStudio2013/mupen64plus-core.vcxproj.filters
View file

@ -264,7 +264,7 @@
<ClCompile Include="..\..\src\device\r4300\instr_counters.c">
<Filter>device\r4300</Filter>
</ClCompile>
<ClCompile Include="..\..\src\device\r4300\interupt.c">
<ClCompile Include="..\..\src\device\r4300\interrupt.c">
<Filter>device\r4300</Filter>
</ClCompile>
<ClCompile Include="..\..\src\device\r4300\mi_controller.c">
@ -632,7 +632,7 @@
<ClInclude Include="..\..\src\device\r4300\instr_counters.h">
<Filter>device\r4300</Filter>
</ClInclude>
<ClInclude Include="..\..\src\device\r4300\interupt.h">
<ClInclude Include="..\..\src\device\r4300\interrupt.h">
<Filter>device\r4300</Filter>
</ClInclude>
<ClInclude Include="..\..\src\device\r4300\macros.h">
@ -781,4 +781,4 @@
<Filter>device\r4300\x86</Filter>
</CustomBuild>
</ItemGroup>
</Project>
</Project>

2
projects/unix/Makefile
View file

@ -463,7 +463,7 @@ SOURCE = \
$(SRCDIR)/device/r4300/cp1.c \
$(SRCDIR)/device/r4300/exception.c \
$(SRCDIR)/device/r4300/instr_counters.c \
$(SRCDIR)/device/r4300/interupt.c \
$(SRCDIR)/device/r4300/interrupt.c \
$(SRCDIR)/device/r4300/mi_controller.c \
$(SRCDIR)/device/r4300/pure_interp.c \
$(SRCDIR)/device/r4300/r4300_core.c \

2
src/device/ai/ai_controller.c
View file

@ -92,7 +92,7 @@ static void do_dma(struct ai_controller* ai, const struct ai_dma* dma)
/* schedule end of dma event */
cp0_update_count();
add_interupt_event(AI_INT, dma->duration);
add_interrupt_event(AI_INT, dma->duration);
}
static void fifo_push(struct ai_controller* ai)

4
src/device/device.c
View file

@ -107,6 +107,6 @@ void hard_reset_device(struct device* dev)
void soft_reset_device(struct device* dev)
{
/* schedule HW2 interrupt now and an NMI after 1/2 seconds */
add_interupt_event(HW2_INT, 0);
add_interupt_event(NMI_INT, 50000000);
add_interrupt_event(HW2_INT, 0);
add_interrupt_event(NMI_INT, 50000000);
}

10
src/device/pi/pi_controller.c
View file

@ -72,7 +72,7 @@ static void dma_pi_read(struct pi_controller* pi)
/* schedule end of dma interrupt event */
cp0_update_count();
add_interupt_event(PI_INT, 0x1000/*pi->regs[PI_RD_LEN_REG]*/); /* XXX: 0x1000 ??? */
add_interrupt_event(PI_INT, 0x1000/*pi->regs[PI_RD_LEN_REG]*/); /* XXX: 0x1000 ??? */
}
static void dma_pi_write(struct pi_controller* pi)
@ -111,7 +111,7 @@ static void dma_pi_write(struct pi_controller* pi)
/* schedule end of dma interrupt event */
cp0_update_count();
add_interupt_event(PI_INT, /*pi->regs[PI_WR_LEN_REG]*/0x1000); /* XXX: 0x1000 ??? */
add_interrupt_event(PI_INT, /*pi->regs[PI_WR_LEN_REG]*/0x1000); /* XXX: 0x1000 ??? */
return;
}
@ -124,7 +124,7 @@ static void dma_pi_write(struct pi_controller* pi)
/* schedule end of dma interrupt event */
cp0_update_count();
add_interupt_event(PI_INT, 0x1000); /* XXX: 0x1000 ??? */
add_interrupt_event(PI_INT, 0x1000); /* XXX: 0x1000 ??? */
return;
}
@ -144,7 +144,7 @@ static void dma_pi_write(struct pi_controller* pi)
/* schedule end of dma interrupt event */
cp0_update_count();
add_interupt_event(PI_INT, longueur/8);
add_interrupt_event(PI_INT, longueur/8);
return;
}
@ -175,7 +175,7 @@ static void dma_pi_write(struct pi_controller* pi)
/* schedule end of dma interrupt event */
cp0_update_count();
add_interupt_event(PI_INT, longueur/8);
add_interrupt_event(PI_INT, longueur/8);
}

6
src/device/r4300/cached_interp.c
View file

@ -32,7 +32,7 @@
#include "device/memory/memory.h"
#include "device/r4300/cached_interp.h"
#include "device/r4300/exception.h"
#include "device/r4300/interupt.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/macros.h"
#include "device/r4300/ops.h"
#include "device/r4300/recomp.h"
@ -87,7 +87,7 @@
cp0_update_count(); \
} \
g_dev.r4300.cp0.last_addr = *r4300_pc(); \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interupt(); \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interrupt(); \
} \
static void name##_OUT(void) \
{ \
@ -118,7 +118,7 @@
cp0_update_count(); \
} \
g_dev.r4300.cp0.last_addr = *r4300_pc(); \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interupt(); \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interrupt(); \
} \
static void name##_IDLE(void) \
{ \

2
src/device/r4300/cp0.h
View file

@ -24,7 +24,7 @@
#include <stdint.h>
#include "interupt.h"
#include "interrupt.h"
#include "tlb.h"
#include "new_dynarec/new_dynarec.h" /* for NEW_DYNAREC_ARM */

8
src/device/r4300/interpreter_cop0.def
View file

@ -77,7 +77,7 @@ DECLARE_INSTRUCTION(MTC0)
case CP0_COUNT_REG:
cp0_update_count();
g_dev.r4300.cp0.interrupt_unsafe_state = 1;
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interupt();
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interrupt();
g_dev.r4300.cp0.interrupt_unsafe_state = 0;
translate_event_queue(rrt32);
cp0_regs[CP0_COUNT_REG] = rrt32;
@ -88,7 +88,7 @@ DECLARE_INSTRUCTION(MTC0)
case CP0_COMPARE_REG:
cp0_update_count();
remove_event(COMPARE_INT);
add_interupt_event_count(COMPARE_INT, rrt32);
add_interrupt_event_count(COMPARE_INT, rrt32);
cp0_regs[CP0_COMPARE_REG] = rrt32;
cp0_regs[CP0_CAUSE_REG] &= ~CP0_CAUSE_IP7;
break;
@ -101,9 +101,9 @@ DECLARE_INSTRUCTION(MTC0)
cp0_regs[CP0_STATUS_REG] = rrt32;
cp0_update_count();
ADD_TO_PC(1);
check_interupt();
check_interrupt();
g_dev.r4300.cp0.interrupt_unsafe_state = 1;
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interupt();
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interrupt();
g_dev.r4300.cp0.interrupt_unsafe_state = 0;
ADD_TO_PC(-1);
break;

4
src/device/r4300/interpreter_tlb.def
View file

@ -256,7 +256,7 @@ DECLARE_INSTRUCTION(ERET)
generic_jump_to(&g_dev.r4300, cp0_regs[CP0_EPC_REG]);
}
g_dev.r4300.llbit = 0;
check_interupt();
check_interrupt();
g_dev.r4300.cp0.last_addr = PCADDR;
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interupt();
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interrupt();
}

60
src/device/r4300/interupt.c → src/device/r4300/interrupt.c
View file

@ -1,5 +1,5 @@
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Mupen64plus - interupt.c *
* Mupen64plus - interrupt.c *
* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
* Copyright (C) 2002 Hacktarux *
* *
@ -21,7 +21,7 @@
#define M64P_CORE_PROTOTYPES 1
#include "interupt.h"
#include "interrupt.h"
#include <stddef.h>
#include <stdint.h>
@ -124,13 +124,13 @@ static int before_event(unsigned int evt1, unsigned int evt2, int type2)
else return 0;
}
void add_interupt_event(int type, unsigned int delay)
void add_interrupt_event(int type, unsigned int delay)
{
uint32_t* cp0_regs = r4300_cp0_regs();
add_interupt_event_count(type, cp0_regs[CP0_COUNT_REG] + delay);
add_interrupt_event_count(type, cp0_regs[CP0_COUNT_REG] + delay);
}
void add_interupt_event_count(int type, unsigned int count)
void add_interrupt_event_count(int type, unsigned int count)
{
struct node* event;
struct node* e;
@ -196,7 +196,7 @@ void add_interupt_event_count(int type, unsigned int count)
}
}
static void remove_interupt_event(void)
static void remove_interrupt_event(void)
{
struct node* e;
uint32_t* cp0_regs = r4300_cp0_regs();
@ -275,8 +275,8 @@ void translate_event_queue(unsigned int base)
{
e->data.count = (e->data.count - cp0_regs[CP0_COUNT_REG]) + base;
}
add_interupt_event_count(COMPARE_INT, cp0_regs[CP0_COMPARE_REG]);
add_interupt_event_count(SPECIAL_INT, 0);
add_interrupt_event_count(COMPARE_INT, cp0_regs[CP0_COMPARE_REG]);
add_interrupt_event_count(SPECIAL_INT, 0);
}
int save_eventqueue_infos(char *buf)
@ -305,23 +305,23 @@ void load_eventqueue_infos(char *buf)
{
int type = *((unsigned int*)&buf[len]);
unsigned int count = *((unsigned int*)&buf[len+4]);
add_interupt_event_count(type, count);
add_interrupt_event_count(type, count);
len += 8;
}
}
void init_interupt(void)
void init_interrupt(void)
{
g_dev.r4300.cp0.special_done = 1;
g_dev.vi.delay = g_dev.vi.next_vi = 5000;
clear_queue();
add_interupt_event_count(VI_INT, g_dev.vi.next_vi);
add_interupt_event_count(SPECIAL_INT, 0);
add_interrupt_event_count(VI_INT, g_dev.vi.next_vi);
add_interrupt_event_count(SPECIAL_INT, 0);
}
void check_interupt(void)
void check_interrupt(void)
{
struct node* event;
uint32_t* cp0_regs = r4300_cp0_regs();
@ -402,16 +402,16 @@ static void special_int_handler(void)
g_dev.r4300.cp0.special_done = 1;
remove_interupt_event();
add_interupt_event_count(SPECIAL_INT, 0);
remove_interrupt_event();
add_interrupt_event_count(SPECIAL_INT, 0);
}
static void compare_int_handler(void)
{
uint32_t* cp0_regs = r4300_cp0_regs();
remove_interupt_event();
remove_interrupt_event();
cp0_regs[CP0_COUNT_REG]+=g_dev.r4300.cp0.count_per_op;
add_interupt_event_count(COMPARE_INT, cp0_regs[CP0_COMPARE_REG]);
add_interrupt_event_count(COMPARE_INT, cp0_regs[CP0_COMPARE_REG]);
cp0_regs[CP0_COUNT_REG]-=g_dev.r4300.cp0.count_per_op;
raise_maskable_interrupt(CP0_CAUSE_IP7);
@ -421,7 +421,7 @@ static void hw2_int_handler(void)
{
uint32_t* cp0_regs = r4300_cp0_regs();
// Hardware Interrupt 2 -- remove interrupt event from queue
remove_interupt_event();
remove_interrupt_event();
cp0_regs[CP0_STATUS_REG] = (cp0_regs[CP0_STATUS_REG] & ~(CP0_STATUS_SR | CP0_STATUS_TS | UINT32_C(0x00080000))) | CP0_STATUS_IM4;
cp0_regs[CP0_CAUSE_REG] = (cp0_regs[CP0_CAUSE_REG] | CP0_CAUSE_IP4) & ~CP0_CAUSE_EXCCODE_MASK;
@ -433,7 +433,7 @@ static void nmi_int_handler(void)
{
uint32_t* cp0_regs = r4300_cp0_regs();
// Non Maskable Interrupt -- remove interrupt event from queue
remove_interupt_event();
remove_interrupt_event();
// setup r4300 Status flags: reset TS and SR, set BEV, ERL, and SR
cp0_regs[CP0_STATUS_REG] = (cp0_regs[CP0_STATUS_REG] & ~(CP0_STATUS_SR | CP0_STATUS_TS | UINT32_C(0x00080000))) | (CP0_STATUS_ERL | CP0_STATUS_BEV | CP0_STATUS_SR);
cp0_regs[CP0_CAUSE_REG] = 0x00000000;
@ -442,7 +442,7 @@ static void nmi_int_handler(void)
// clear all interrupts, reset interrupt counters back to 0
cp0_regs[CP0_COUNT_REG] = 0;
g_gs_vi_counter = 0;
init_interupt();
init_interrupt();
// clear the audio status register so that subsequent write_ai() calls will work properly
g_dev.ai.regs[AI_STATUS_REG] = 0;
// set ErrorEPC with the last instruction address
@ -485,7 +485,7 @@ static void reset_hard(void)
pifbootrom_hle_execute(&g_dev);
g_dev.r4300.cp0.last_addr = UINT32_C(0xa4000040);
*r4300_cp0_next_interrupt() = 624999;
init_interupt();
init_interrupt();
if(g_dev.r4300.emumode != EMUMODE_PURE_INTERPRETER)
{
free_blocks(&g_dev.r4300.cached_interp);
@ -495,7 +495,7 @@ static void reset_hard(void)
}
void gen_interupt(void)
void gen_interrupt(void)
{
uint32_t* cp0_regs = r4300_cp0_regs();
unsigned int* cp0_next_interrupt = r4300_cp0_next_interrupt();
@ -543,7 +543,7 @@ void gen_interupt(void)
break;
case VI_INT:
remove_interupt_event();
remove_interrupt_event();
vi_vertical_interrupt_event(&g_dev.vi);
break;
@ -552,32 +552,32 @@ void gen_interupt(void)
break;
case CHECK_INT:
remove_interupt_event();
remove_interrupt_event();
wrapped_exception_general();
break;
case SI_INT:
remove_interupt_event();
remove_interrupt_event();
si_end_of_dma_event(&g_dev.si);
break;
case PI_INT:
remove_interupt_event();
remove_interrupt_event();
pi_end_of_dma_event(&g_dev.pi);
break;
case AI_INT:
remove_interupt_event();
remove_interrupt_event();
ai_end_of_dma_event(&g_dev.ai);
break;
case SP_INT:
remove_interupt_event();
remove_interrupt_event();
rsp_interrupt_event(&g_dev.sp);
break;
case DP_INT:
remove_interupt_event();
remove_interrupt_event();
rdp_interrupt_event(&g_dev.dp);
break;
@ -591,7 +591,7 @@ void gen_interupt(void)
default:
DebugMessage(M64MSG_ERROR, "Unknown interrupt queue event type %.8X.", g_dev.r4300.cp0.q.first->data.type);
remove_interupt_event();
remove_interrupt_event();
wrapped_exception_general();
break;
}

18
src/device/r4300/interupt.h → src/device/r4300/interrupt.h
View file

@ -1,5 +1,5 @@
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* Mupen64plus - interupt.h *
* Mupen64plus - interrupt.h *
* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
* Copyright (C) 2002 Hacktarux *
* *
@ -19,22 +19,22 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
#ifndef M64P_DEVICE_R4300_INTERUPT_H
#define M64P_DEVICE_R4300_INTERUPT_H
#ifndef M64P_DEVICE_R4300_INTERRUPT_H
#define M64P_DEVICE_R4300_INTERRUPT_H
#include <stdint.h>
void init_interupt(void);
void init_interrupt(void);
void raise_maskable_interrupt(uint32_t cause);
void gen_interupt(void);
void check_interupt(void);
void gen_interrupt(void);
void check_interrupt(void);
void translate_event_queue(unsigned int base);
void remove_event(int type);
void add_interupt_event_count(int type, unsigned int count);
void add_interupt_event(int type, unsigned int delay);
void add_interrupt_event_count(int type, unsigned int count);
void add_interrupt_event(int type, unsigned int delay);
unsigned int get_event(int type);
int get_next_event_type(void);
@ -53,4 +53,4 @@ void load_eventqueue_infos(char *buf);
#define HW2_INT 0x200
#define NMI_INT 0x400
#endif /* M64P_DEVICE_R4300_INTERUPT_H */
#endif /* M64P_DEVICE_R4300_INTERRUPT_H */

10
src/device/r4300/mi_controller.c
View file

@ -24,7 +24,7 @@
#include <string.h>
#include "cp0.h"
#include "interupt.h"
#include "interrupt.h"
#include "r4300_core.h"
static int update_mi_init_mode(uint32_t* mi_init_mode, uint32_t w)
@ -101,9 +101,9 @@ int write_mi_regs(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
case MI_INTR_MASK_REG:
update_mi_intr_mask(&r4300->mi.regs[MI_INTR_MASK_REG], value & mask);
check_interupt();
check_interrupt();
cp0_update_count();
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interupt();
if (*cp0_next_interrupt <= cp0_regs[CP0_COUNT_REG]) gen_interrupt();
break;
}
@ -123,12 +123,12 @@ void raise_rcp_interrupt(struct r4300_core* r4300, uint32_t mi_intr)
void signal_rcp_interrupt(struct r4300_core* r4300, uint32_t mi_intr)
{
r4300->mi.regs[MI_INTR_REG] |= mi_intr;
check_interupt();
check_interrupt();
}
void clear_rcp_interrupt(struct r4300_core* r4300, uint32_t mi_intr)
{
r4300->mi.regs[MI_INTR_REG] &= ~mi_intr;
check_interupt();
check_interrupt();
}

4
src/device/r4300/new_dynarec/arm/linkage_arm.S
View file

@ -290,7 +290,7 @@ GLOBAL_FUNCTION(cc_interrupt):
tst r4, r4
bne .E4
.E1:
bl gen_interupt
bl gen_interrupt
mov lr, r10
ldr r10, [fp, #g_dev_r4300_cp0_regs+36-dynarec_local] /* Count */
ldr r0, [fp, #g_dev_r4300_cp0_next_interrupt-dynarec_local]
@ -379,7 +379,7 @@ GLOBAL_FUNCTION(jump_eret):
add r10, r0, r10
str r1, [fp, #g_dev_r4300_cp0_regs+48-dynarec_local] /* Status */
str r10, [fp, #g_dev_r4300_cp0_regs+36-dynarec_local] /* Count */
bl check_interupt
bl check_interrupt
ldr r1, [fp, #g_dev_r4300_cp0_next_interrupt-dynarec_local]
ldr r0, [fp, #g_dev_r4300_cp0_regs+56-dynarec_local] /* EPC */
str r1, [fp, #last_count-dynarec_local]

4
src/device/r4300/new_dynarec/new_dynarec.c
View file

@ -36,7 +36,7 @@
#include "device/rsp/rsp_core.h"
#include "device/r4300/cached_interp.h"
#include "device/r4300/cp1.h"
#include "device/r4300/interupt.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/ops.h"
#include "device/r4300/recomp.h"
#include "device/r4300/tlb.h"
@ -5989,7 +5989,7 @@ static void do_ccstub(int n)
emit_readword((int)&last_count,ECX);
emit_add(HOST_CCREG,ECX,EAX);
emit_writeword(EAX,(int)&r4300_cp0_regs()[CP0_COUNT_REG]);
emit_call((int)gen_interupt);
emit_call((int)gen_interrupt);
emit_readword((int)&r4300_cp0_regs()[CP0_COUNT_REG],HOST_CCREG);
emit_readword((int)&g_dev.r4300.cp0.next_interrupt,EAX);
emit_readword((int)&pending_exception,EBX);

8
src/device/r4300/new_dynarec/x86/linkage_x86.asm
View file

@ -119,13 +119,13 @@ cextern branch_target
cextern memory_map
cextern pending_exception
cextern restore_candidate
cextern gen_interupt
cextern gen_interrupt
cextern last_count
cextern pcaddr
cextern clean_blocks
cextern invalidate_block
cextern readmem_dword
cextern check_interupt
cextern check_interrupt
cextern get_addr_32
cextern write_mi
cextern write_mib
@ -257,7 +257,7 @@ cc_interrupt:
cmp DWORD [find_local_data(restore_candidate+esi)], 0
jne _E4
_E1:
call gen_interupt
call gen_interrupt
mov esi, [find_local_data(g_dev_r4300_cp0_regs+36)]
mov eax, [find_local_data(g_dev_r4300_cp0_next_interrupt)]
mov edx, [find_local_data(pending_exception)]
@ -360,7 +360,7 @@ jump_eret:
and ecx, 0FFFFFFFDh
mov [find_local_data(g_dev_r4300_cp0_regs+36)], esi ;Count
mov [find_local_data(g_dev_r4300_cp0_regs+48)], ecx ;Status
call check_interupt
call check_interrupt
mov eax, [find_local_data(g_dev_r4300_cp0_next_interrupt)]
mov esi, [find_local_data(g_dev_r4300_cp0_regs+36)]
mov [find_local_data(last_count)], eax

4
src/device/r4300/pure_interp.c
View file

@ -33,7 +33,7 @@
#include "device/r4300/cached_interp.h"
#include "device/r4300/cp1.h"
#include "device/r4300/exception.h"
#include "device/r4300/interupt.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/tlb.h"
#include "main/main.h"
#include "osal/preproc.h"
@ -78,7 +78,7 @@ static void InterpretOpcode(void);
cp0_update_count(); \
} \
g_dev.r4300.cp0.last_addr = g_dev.r4300.interp_PC.addr; \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interupt(); \
if (*r4300_cp0_next_interrupt() <= r4300_cp0_regs()[CP0_COUNT_REG]) gen_interrupt(); \
} \
static void name##_IDLE(uint32_t op) \
{ \

2
src/device/r4300/r4300_core.c
View file

@ -141,7 +141,7 @@ void run_r4300(struct r4300_core* r4300)
/* XXX: might go to r4300_poweron / soft_reset ? */
r4300->cp0.last_addr = 0xa4000040;
*r4300_cp0_next_interrupt() = 624999;
init_interupt();
init_interrupt();
if (r4300->emumode == EMUMODE_PURE_INTERPRETER)
{

2
src/device/r4300/recomph.h
View file

@ -273,7 +273,7 @@ void gensdl(void);
void gensdr(void);
void genlink_subblock(void);
void gendelayslot(void);
void gencheck_interupt_reg(void);
void gencheck_interrupt_reg(void);
void gentest(void);
void gentest_out(void);
void gentest_idle(void);

38
src/device/r4300/x86/gr4300.c
View file

@ -27,7 +27,7 @@
#include "device/r4300/cached_interp.h"
#include "device/r4300/cp1.h"
#include "device/r4300/exception.h"
#include "device/r4300/interupt.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/ops.h"
#include "device/r4300/recomph.h"
#include "main/main.h"
@ -50,24 +50,24 @@ static void gencp0_update_count(unsigned int addr)
#endif
}
static void gencheck_interupt(unsigned int instr_structure)
static void gencheck_interrupt(unsigned int instr_structure)
{
mov_eax_memoffs32(r4300_cp0_next_interrupt());
cmp_reg32_m32(EAX, &r4300_cp0_regs()[CP0_COUNT_REG]);
ja_rj(17);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), instr_structure); // 10
mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
mov_reg32_imm32(EAX, (unsigned int)gen_interrupt); // 5
call_reg32(EAX); // 2
}
static void gencheck_interupt_out(unsigned int addr)
static void gencheck_interrupt_out(unsigned int addr)
{
mov_eax_memoffs32(r4300_cp0_next_interrupt());
cmp_reg32_m32(EAX, &r4300_cp0_regs()[CP0_COUNT_REG]);
ja_rj(27);
mov_m32_imm32((unsigned int*)(&g_dev.r4300.fake_instr.addr), addr);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(&g_dev.r4300.fake_instr));
mov_reg32_imm32(EAX, (unsigned int)gen_interupt);
mov_reg32_imm32(EAX, (unsigned int)gen_interrupt);
call_reg32(EAX);
}
@ -384,14 +384,14 @@ void genfin_block(void)
gencallinterp((unsigned int)cached_interpreter_table.FIN_BLOCK, 0);
}
void gencheck_interupt_reg(void) // addr is in EAX
void gencheck_interrupt_reg(void) // addr is in EAX
{
mov_reg32_m32(EBX, r4300_cp0_next_interrupt());
cmp_reg32_m32(EBX, &r4300_cp0_regs()[CP0_COUNT_REG]);
ja_rj(22);
mov_memoffs32_eax((unsigned int*)(&g_dev.r4300.fake_instr.addr)); // 5
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(&g_dev.r4300.fake_instr)); // 10
mov_reg32_imm32(EAX, (unsigned int)gen_interupt); // 5
mov_reg32_imm32(EAX, (unsigned int)gen_interrupt); // 5
call_reg32(EAX); // 2
}
@ -417,7 +417,7 @@ void genj(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, naddr);
gencheck_interupt((unsigned int)&g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
gencheck_interrupt((unsigned int)&g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
jmp(naddr);
#endif
}
@ -440,7 +440,7 @@ void genj_out(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, naddr);
gencheck_interupt_out(naddr);
gencheck_interrupt_out(naddr);
mov_m32_imm32(&g_dev.r4300.recomp.jump_to_address, naddr);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(g_dev.r4300.recomp.dst+1));
mov_reg32_imm32(EAX, (unsigned int)dynarec_jump_to_address);
@ -497,7 +497,7 @@ void genjal(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, naddr);
gencheck_interupt((unsigned int)&g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
gencheck_interrupt((unsigned int)&g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
jmp(naddr);
#endif
}
@ -527,7 +527,7 @@ void genjal_out(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, naddr);
gencheck_interupt_out(naddr);
gencheck_interrupt_out(naddr);
mov_m32_imm32(&g_dev.r4300.recomp.jump_to_address, naddr);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(g_dev.r4300.recomp.dst+1));
mov_reg32_imm32(EAX, (unsigned int)dynarec_jump_to_address);
@ -567,13 +567,13 @@ void gentest(void)
jump_start_rel32();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
jmp(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
jump_end_rel32();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -603,7 +603,7 @@ void gentest_out(void)
jump_start_rel32();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interrupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32_imm32(&g_dev.r4300.recomp.jump_to_address, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(g_dev.r4300.recomp.dst+1));
mov_reg32_imm32(EAX, (unsigned int)dynarec_jump_to_address);
@ -612,7 +612,7 @@ void gentest_out(void)
jump_end_rel32();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -971,14 +971,14 @@ void gentestl(void)
gendelayslot();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
jmp(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
jump_end_rel32();
gencp0_update_count(g_dev.r4300.recomp.dst->addr+4);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -1009,7 +1009,7 @@ void gentestl_out(void)
gendelayslot();
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interrupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32_imm32(&g_dev.r4300.recomp.jump_to_address, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32_imm32((unsigned int*)(&(*r4300_pc_struct())), (unsigned int)(g_dev.r4300.recomp.dst+1));
mov_reg32_imm32(EAX, (unsigned int)dynarec_jump_to_address);
@ -1019,7 +1019,7 @@ void gentestl_out(void)
gencp0_update_count(g_dev.r4300.recomp.dst->addr+4);
mov_m32_imm32(&g_dev.r4300.cp0.last_addr, g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned int)(g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}

4
src/device/r4300/x86/gspecial.c
View file

@ -181,7 +181,7 @@ void genjr(void)
mov_eax_memoffs32((unsigned int *)&g_dev.r4300.local_rs);
mov_memoffs32_eax((unsigned int *)&g_dev.r4300.cp0.last_addr);
gencheck_interupt_reg();
gencheck_interrupt_reg();
mov_eax_memoffs32((unsigned int *)&g_dev.r4300.local_rs);
mov_reg32_reg32(EBX, EAX);
@ -252,7 +252,7 @@ void genjalr(void)
mov_eax_memoffs32((unsigned int *)&g_dev.r4300.local_rs);
mov_memoffs32_eax((unsigned int *)&g_dev.r4300.cp0.last_addr);
gencheck_interupt_reg();
gencheck_interrupt_reg();
mov_eax_memoffs32((unsigned int *)&g_dev.r4300.local_rs);
mov_reg32_reg32(EBX, EAX);

38
src/device/r4300/x86_64/gr4300.c
View file

@ -31,7 +31,7 @@
#include "device/r4300/cached_interp.h"
#include "device/r4300/cp1.h"
#include "device/r4300/exception.h"
#include "device/r4300/interupt.h"
#include "device/r4300/interrupt.h"
#include "device/r4300/ops.h"
#include "device/r4300/recomp.h"
#include "device/r4300/recomph.h"
@ -64,7 +64,7 @@ static void gencp0_update_count(unsigned int addr)
#endif
}
static void gencheck_interupt(unsigned long long instr_structure)
static void gencheck_interrupt(unsigned long long instr_structure)
{
mov_xreg32_m32rel(EAX, (void*)(r4300_cp0_next_interrupt()));
cmp_xreg32_m32rel(EAX, (void*)&r4300_cp0_regs()[CP0_COUNT_REG]);
@ -73,13 +73,13 @@ static void gencheck_interupt(unsigned long long instr_structure)
mov_reg64_imm64(RAX, (unsigned long long) instr_structure);
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
mov_reg64_imm64(RAX, (unsigned long long) gen_interrupt);
call_reg64(RAX);
jump_end_rel8();
}
static void gencheck_interupt_out(unsigned int addr)
static void gencheck_interrupt_out(unsigned int addr)
{
mov_xreg32_m32rel(EAX, (void*)(r4300_cp0_next_interrupt()));
cmp_xreg32_m32rel(EAX, (void*)&r4300_cp0_regs()[CP0_COUNT_REG]);
@ -89,7 +89,7 @@ static void gencheck_interupt_out(unsigned int addr)
mov_m32rel_imm32((unsigned int*)(&g_dev.r4300.fake_instr.addr), addr);
mov_reg64_imm64(RAX, (unsigned long long) (&g_dev.r4300.fake_instr));
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
mov_reg64_imm64(RAX, (unsigned long long) gen_interrupt);
call_reg64(RAX);
jump_end_rel8();
@ -356,7 +356,7 @@ void genfin_block(void)
gencallinterp((unsigned long long)cached_interpreter_table.FIN_BLOCK, 0);
}
void gencheck_interupt_reg(void) // addr is in EAX
void gencheck_interrupt_reg(void) // addr is in EAX
{
mov_xreg32_m32rel(EBX, (void*)r4300_cp0_next_interrupt());
cmp_xreg32_m32rel(EBX, (void*)&r4300_cp0_regs()[CP0_COUNT_REG]);
@ -366,7 +366,7 @@ void gencheck_interupt_reg(void) // addr is in EAX
mov_m32rel_xreg32((unsigned int*)(&g_dev.r4300.fake_instr.addr), EAX);
mov_reg64_imm64(RAX, (unsigned long long) (&g_dev.r4300.fake_instr));
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
mov_reg64_imm64(RAX, (unsigned long long) gen_interupt);
mov_reg64_imm64(RAX, (unsigned long long) gen_interrupt);
call_reg64(RAX);
jump_end_rel8();
@ -397,7 +397,7 @@ void genj(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), naddr);
gencheck_interupt((unsigned long long) &g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
gencheck_interrupt((unsigned long long) &g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
jmp(naddr);
#endif
}
@ -423,7 +423,7 @@ void genj_out(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), naddr);
gencheck_interupt_out(naddr);
gencheck_interrupt_out(naddr);
mov_m32rel_imm32(&g_dev.r4300.recomp.jump_to_address, naddr);
mov_reg64_imm64(RAX, (unsigned long long) (g_dev.r4300.recomp.dst+1));
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
@ -487,7 +487,7 @@ void genjal(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), naddr);
gencheck_interupt((unsigned long long) &g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
gencheck_interrupt((unsigned long long) &g_dev.r4300.cached_interp.actual->block[(naddr-g_dev.r4300.cached_interp.actual->start)/4]);
jmp(naddr);
#endif
}
@ -520,7 +520,7 @@ void genjal_out(void)
naddr = ((g_dev.r4300.recomp.dst-1)->f.j.inst_index<<2) | (g_dev.r4300.recomp.dst->addr & 0xF0000000);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), naddr);
gencheck_interupt_out(naddr);
gencheck_interrupt_out(naddr);
mov_m32rel_imm32(&g_dev.r4300.recomp.jump_to_address, naddr);
mov_reg64_imm64(RAX, (unsigned long long) (g_dev.r4300.recomp.dst+1));
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
@ -563,13 +563,13 @@ void gentest(void)
jump_start_rel32();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt((unsigned long long) (g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
gencheck_interrupt((unsigned long long) (g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
jmp(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
jump_end_rel32();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned long long)(g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned long long)(g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -601,7 +601,7 @@ void gentest_out(void)
jump_start_rel32();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interrupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32rel_imm32(&g_dev.r4300.recomp.jump_to_address, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_reg64_imm64(RAX, (unsigned long long) (g_dev.r4300.recomp.dst+1));
mov_m64rel_xreg64((unsigned long long *)(&(*r4300_pc_struct())), RAX);
@ -610,7 +610,7 @@ void gentest_out(void)
jump_end_rel32();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -995,14 +995,14 @@ void gentestl(void)
gendelayslot();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt((unsigned long long) (g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
gencheck_interrupt((unsigned long long) (g_dev.r4300.recomp.dst + (g_dev.r4300.recomp.dst-1)->f.i.immediate));
jmp(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
jump_end_rel32();
gencp0_update_count(g_dev.r4300.recomp.dst->addr-4);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}
@ -1035,7 +1035,7 @@ void gentestl_out(void)
gendelayslot();
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
gencheck_interrupt_out(g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_m32rel_imm32(&g_dev.r4300.recomp.jump_to_address, g_dev.r4300.recomp.dst->addr + (g_dev.r4300.recomp.dst-1)->f.i.immediate*4);
mov_reg64_imm64(RAX, (unsigned long long) (g_dev.r4300.recomp.dst+1));
@ -1047,7 +1047,7 @@ void gentestl_out(void)
gencp0_update_count(g_dev.r4300.recomp.dst->addr-4);
mov_m32rel_imm32((void*)(&g_dev.r4300.cp0.last_addr), g_dev.r4300.recomp.dst->addr + 4);
gencheck_interupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
gencheck_interrupt((unsigned long long) (g_dev.r4300.recomp.dst + 1));
jmp(g_dev.r4300.recomp.dst->addr + 4);
}

4
src/device/r4300/x86_64/gspecial.c
View file

@ -210,7 +210,7 @@ void genjr(void)
mov_xreg32_m32rel(EAX, (unsigned int *)&g_dev.r4300.local_rs);
mov_m32rel_xreg32((unsigned int *)&g_dev.r4300.cp0.last_addr, EAX);
gencheck_interupt_reg();
gencheck_interrupt_reg();
mov_xreg32_m32rel(EAX, (unsigned int *)&g_dev.r4300.local_rs);
mov_reg32_reg32(EBX, EAX);
@ -284,7 +284,7 @@ void genjalr(void)
mov_xreg32_m32rel(EAX, (unsigned int *)&g_dev.r4300.local_rs);
mov_m32rel_xreg32((unsigned int *)&g_dev.r4300.cp0.last_addr, EAX);
gencheck_interupt_reg();
gencheck_interrupt_reg();
mov_xreg32_m32rel(EAX, (unsigned int *)&g_dev.r4300.local_rs);
mov_reg32_reg32(EBX, EAX);

8
src/device/rsp/rsp_core.c
View file

@ -285,9 +285,9 @@ void do_SP_Task(struct rsp_core* sp)
cp0_update_count();
if (sp->r4300->mi.regs[MI_INTR_REG] & MI_INTR_SP)
add_interupt_event(SP_INT, 1000);
add_interrupt_event(SP_INT, 1000);
if (sp->r4300->mi.regs[MI_INTR_REG] & MI_INTR_DP)
add_interupt_event(DP_INT, 1000);
add_interrupt_event(DP_INT, 1000);
sp->r4300->mi.regs[MI_INTR_REG] &= ~(MI_INTR_SP | MI_INTR_DP);
sp->regs[SP_STATUS_REG] &= ~SP_STATUS_TASKDONE;
@ -304,7 +304,7 @@ void do_SP_Task(struct rsp_core* sp)
cp0_update_count();
if (sp->r4300->mi.regs[MI_INTR_REG] & MI_INTR_SP)
add_interupt_event(SP_INT, 4000/*500*/);
add_interrupt_event(SP_INT, 4000/*500*/);
sp->r4300->mi.regs[MI_INTR_REG] &= ~MI_INTR_SP;
sp->regs[SP_STATUS_REG] &= ~(SP_STATUS_TASKDONE | SP_STATUS_YIELDED);
}
@ -316,7 +316,7 @@ void do_SP_Task(struct rsp_core* sp)
cp0_update_count();
if (sp->r4300->mi.regs[MI_INTR_REG] & MI_INTR_SP)
add_interupt_event(SP_INT, 0/*100*/);
add_interrupt_event(SP_INT, 0/*100*/);
sp->r4300->mi.regs[MI_INTR_REG] &= ~MI_INTR_SP;
sp->regs[SP_STATUS_REG] &= ~SP_STATUS_TASKDONE;
}

2
src/device/si/pif.c
View file

@ -143,7 +143,7 @@ int write_pif_ram(void* opaque, uint32_t address, uint32_t value, uint32_t mask)
{
si->pif.ram[0x3f] = 0;
cp0_update_count();
add_interupt_event(SI_INT, /*0x100*/0x900);
add_interrupt_event(SI_INT, /*0x100*/0x900);
}
else
{

4
src/device/si/si_controller.c
View file

@ -56,7 +56,7 @@ static void dma_si_write(struct si_controller* si)
cp0_update_count();
if (g_delay_si) {
add_interupt_event(SI_INT, /*0x100*/0x900);
add_interrupt_event(SI_INT, /*0x100*/0x900);
} else {
si->regs[SI_STATUS_REG] |= SI_STATUS_INTERRUPT;
signal_rcp_interrupt(si->r4300, MI_INTR_SI);
@ -83,7 +83,7 @@ static void dma_si_read(struct si_controller* si)
cp0_update_count();
if (g_delay_si) {
add_interupt_event(SI_INT, /*0x100*/0x900);
add_interrupt_event(SI_INT, /*0x100*/0x900);
} else {
si->regs[SI_STATUS_REG] |= SI_STATUS_INTERRUPT;
signal_rcp_interrupt(si->r4300, MI_INTR_SI);

2
src/device/vi/vi_controller.c
View file

@ -153,7 +153,7 @@ void vi_vertical_interrupt_event(struct vi_controller* vi)
vi->next_vi += vi->delay;
add_interupt_event_count(VI_INT, vi->next_vi);
add_interrupt_event_count(VI_INT, vi->next_vi);
/* trigger interrupt */
raise_rcp_interrupt(vi->r4300, MI_INTR_VI);

2
src/main/savestates.c
View file

@ -591,7 +591,7 @@ static int savestates_load_pj64(char *filepath, void *handle,
if ((cp0_regs[CP0_STATUS_REG] & UINT32_C(0x04000000)) == 0) // TODO not sure how pj64 handles this
shuffle_fpr_data(UINT32_C(0x04000000), 0);
// Initialze the interupts
// Initialze the interrupts
vi_timer += cp0_regs[CP0_COUNT_REG];
*r4300_cp0_next_interrupt() = (cp0_regs[CP0_COMPARE_REG] < vi_timer)
? cp0_regs[CP0_COMPARE_REG]

6
tools/savestate_convert.c
View file

@ -84,7 +84,7 @@ char FCR31[4];
char tlb_e[32][SIZE_TLB_ENTRY];
char PCaddr[4];
char next_interupt[4];
char next_interrupt[4];
char next_vi[4];
char vi_field[4];
@ -299,7 +299,7 @@ int load_original_mupen64(const char *filename)
gzread(f, tlb_e[0], 32 * SIZE_TLB_ENTRY);
gzread(f, PCaddr, 4);
gzread(f, next_interupt, 4);
gzread(f, next_interrupt, 4);
gzread(f, next_vi, 4);
gzread(f, vi_field, 4);
@ -384,7 +384,7 @@ int save_newest(const char *filename)
gzwrite(f, tlb_e[0], 32 * SIZE_TLB_ENTRY);
gzwrite(f, PCaddr, 4);
gzwrite(f, next_interupt, 4);
gzwrite(f, next_interrupt, 4);
gzwrite(f, next_vi, 4);
gzwrite(f, vi_field, 4);