mirror of
https://github.com/hch12907/orbum.git
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296 lines
9.1 KiB
C++
296 lines
9.1 KiB
C++
#pragma once
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#include <cereal/cereal.hpp>
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#include <cereal/types/polymorphic.hpp>
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#include "Common/Types/Mips/MipsCoprocessor0.hpp"
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#include "Common/Types/Register/SizedWordRegister.hpp"
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/// EE COP0 registers.
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/// See EE Core Users Manual page 62 onwards for more information.
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class EeCoreCop0Register_Index : public SizedWordRegister
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{
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public:
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static constexpr Bitfield INDEX = Bitfield(0, 6);
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static constexpr Bitfield P = Bitfield(31, 1);
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};
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class EeCoreCop0Register_Random : public SizedWordRegister
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{
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public:
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static constexpr Bitfield RANDOM = Bitfield(0, 6);
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static constexpr uword INITIAL_VALUE = 47;
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EeCoreCop0Register_Random();
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};
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class EeCoreCop0Register_EntryLo0 : public SizedWordRegister
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{
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public:
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static constexpr Bitfield G = Bitfield(0, 1);
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static constexpr Bitfield V = Bitfield(1, 1);
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static constexpr Bitfield D = Bitfield(2, 1);
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static constexpr Bitfield C = Bitfield(3, 3);
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static constexpr Bitfield PFN = Bitfield(6, 20);
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static constexpr Bitfield S = Bitfield(31, 1);
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};
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class EeCoreCop0Register_EntryLo1 : public SizedWordRegister
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{
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public:
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static constexpr Bitfield G = Bitfield(0, 1);
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static constexpr Bitfield V = Bitfield(1, 1);
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static constexpr Bitfield D = Bitfield(2, 1);
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static constexpr Bitfield C = Bitfield(3, 3);
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static constexpr Bitfield PFN = Bitfield(6, 20);
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};
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class EeCoreCop0Register_System : public SizedWordRegister
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{
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public:
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static constexpr Bitfield BADVPN2 = Bitfield(4, 19);
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static constexpr Bitfield PTEBASE = Bitfield(23, 9);
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};
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class EeCoreCop0Register_PageMask : public SizedWordRegister
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{
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public:
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static constexpr Bitfield MASK = Bitfield(13, 12);
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};
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class EeCoreCop0Register_Wired : public SizedWordRegister
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{
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public:
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static constexpr Bitfield Wired = Bitfield(0, 6);
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};
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class EeCoreCop0Register_EntryHi : public SizedWordRegister
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{
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public:
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static constexpr Bitfield ASID = Bitfield(0, 8);
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static constexpr Bitfield VPN2 = Bitfield(13, 19);
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};
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class EeCoreCop0Register_Status : public SizedWordRegister
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{
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public:
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static constexpr Bitfield IE = Bitfield(0, 1);
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static constexpr Bitfield EXL = Bitfield(1, 1);
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static constexpr Bitfield ERL = Bitfield(2, 1);
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static constexpr Bitfield KSU = Bitfield(3, 2);
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static constexpr Bitfield IM = Bitfield(8, 8);
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static constexpr Bitfield EIE = Bitfield(16, 1);
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static constexpr Bitfield EDI = Bitfield(17, 1);
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static constexpr Bitfield CH = Bitfield(18, 1);
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static constexpr Bitfield BEV = Bitfield(22, 1);
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static constexpr Bitfield DEV = Bitfield(23, 1);
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static constexpr Bitfield CU = Bitfield(28, 4);
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static constexpr uword INITIAL_VALUE = 0x00400004; // BEV = 1, ERL = 1.
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EeCoreCop0Register_Status();
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/// Upon writes:
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/// - Caches the operating context for COP0.
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/// - Caches the interrupt masked state for the CPU.
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/// - Caches the internal Count register interrupt state.
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void write_uword(const uword value) override;
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/// Current cached CPU interrupts masked state.
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bool interrupts_masked;
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/// Current cached COP0 operating context state.
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MipsCoprocessor0::OperatingContext operating_context;
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/// Current cached Count register interrupt state.
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bool count_interrupts_enabled;
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private:
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/// Updates the cached interrupt masked state.
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/// Does so by checking the master ERL, EXL, EIE and IE bit.
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void handle_interrupts_masked_update();
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/// Updates the operation context state.
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/// Uses the KSU, ERL and EXL bits.
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void handle_operating_context_update();
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/// Updates the count interrupt state.
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void handle_count_interrupt_state_update();
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public:
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template <class Archive>
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void serialize(Archive& archive)
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{
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archive(
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cereal::base_class<SizedWordRegister>(this),
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CEREAL_NVP(interrupts_masked),
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CEREAL_NVP(operating_context),
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CEREAL_NVP(count_interrupts_enabled));
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}
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};
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/// Cause register.
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/// As this is accessed by other peripherals, the IP bits should only be changed
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/// (externally) using set/clear_irq_line(), which uses separate flags. When the
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/// EE Core reads from the register, the flags will be substituted into the read.
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/// The reason for this is to prevent missed register updates.
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class EeCoreCop0Register_Cause : public SizedWordRegister
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{
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public:
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static constexpr Bitfield EXCCODE = Bitfield(2, 5);
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static constexpr Bitfield IP = Bitfield(8, 8);
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static constexpr Bitfield EXC2 = Bitfield(16, 3);
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static constexpr Bitfield CE = Bitfield(28, 2);
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static constexpr Bitfield BD2 = Bitfield(30, 1);
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static constexpr Bitfield BD = Bitfield(31, 1);
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EeCoreCop0Register_Cause();
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/// Clears all of the IRQ lines.
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void clear_all_irq();
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/// Sets the given IRQ line.
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void set_irq_line(const int irq);
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/// Clears the given IRQ line.
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void clear_irq_line(const int irq);
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/// Syncs the register state with the IRQ flags and returns the register value.
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uword read_uword() override;
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private:
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/// IRQ line flags.
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bool irq_lines[8];
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public:
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template <class Archive>
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void serialize(Archive& archive)
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{
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archive(
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cereal::base_class<SizedWordRegister>(this),
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CEREAL_NVP(irq_lines));
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}
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};
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class EeCoreCop0Register_Prid : public SizedWordRegister
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{
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public:
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static constexpr Bitfield REV = Bitfield(0, 8);
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static constexpr Bitfield IMP = Bitfield(8, 8);
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static constexpr uword INITIAL_VALUE = 0x00002E20;
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EeCoreCop0Register_Prid();
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};
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class EeCoreCop0Register_Config : public SizedWordRegister
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{
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public:
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static constexpr Bitfield K0 = Bitfield(0, 3);
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static constexpr Bitfield DC = Bitfield(6, 3);
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static constexpr Bitfield IC = Bitfield(9, 3);
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static constexpr Bitfield BPE = Bitfield(12, 1);
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static constexpr Bitfield NBE = Bitfield(13, 1);
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static constexpr Bitfield DCE = Bitfield(16, 1);
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static constexpr Bitfield ICE = Bitfield(17, 1);
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static constexpr Bitfield DIE = Bitfield(18, 1);
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static constexpr Bitfield EC = Bitfield(28, 3);
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static constexpr uword INITIAL_VALUE = 0x00000440;
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EeCoreCop0Register_Config();
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};
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class EeCoreCop0Register_BadPAddr : public SizedWordRegister
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{
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public:
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static constexpr Bitfield BadPAddr = Bitfield(4, 28);
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};
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class EeCoreCop0Register_Bpc : public SizedWordRegister
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{
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public:
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static constexpr Bitfield IAB = Bitfield(0, 1);
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static constexpr Bitfield DRB = Bitfield(1, 1);
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static constexpr Bitfield DWB = Bitfield(2, 1);
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static constexpr Bitfield BED = Bitfield(15, 1);
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static constexpr Bitfield DTE = Bitfield(16, 1);
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static constexpr Bitfield ITE = Bitfield(17, 1);
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static constexpr Bitfield DXE = Bitfield(18, 1);
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static constexpr Bitfield DKE = Bitfield(19, 1);
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static constexpr Bitfield DSE = Bitfield(20, 1);
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static constexpr Bitfield DUE = Bitfield(21, 1);
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static constexpr Bitfield IXE = Bitfield(23, 1);
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static constexpr Bitfield IKE = Bitfield(24, 1);
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static constexpr Bitfield ISE = Bitfield(25, 1);
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static constexpr Bitfield IUE = Bitfield(26, 1);
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static constexpr Bitfield DVE = Bitfield(28, 1);
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static constexpr Bitfield DWE = Bitfield(29, 1);
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static constexpr Bitfield DRE = Bitfield(30, 1);
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static constexpr Bitfield IAE = Bitfield(31, 1);
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};
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class EeCoreCop0Register_Pccr : public SizedWordRegister
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{
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public:
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static constexpr Bitfield EXL0 = Bitfield(1, 1);
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static constexpr Bitfield K0 = Bitfield(2, 1);
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static constexpr Bitfield S0 = Bitfield(3, 1);
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static constexpr Bitfield U0 = Bitfield(4, 1);
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static constexpr Bitfield EVENT0 = Bitfield(5, 5);
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static constexpr Bitfield EXL1 = Bitfield(11, 1);
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static constexpr Bitfield K1 = Bitfield(12, 1);
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static constexpr Bitfield S1 = Bitfield(13, 1);
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static constexpr Bitfield U1 = Bitfield(14, 1);
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static constexpr Bitfield EVENT1 = Bitfield(15, 5);
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static constexpr Bitfield CTE = Bitfield(31, 1);
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};
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class EeCoreCop0Register_Pcr0 : public SizedWordRegister
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{
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public:
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static constexpr Bitfield VALUE = Bitfield(0, 31);
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static constexpr Bitfield OVFL = Bitfield(31, 1);
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};
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class EeCoreCop0Register_Pcr1 : public SizedWordRegister
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{
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public:
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static constexpr Bitfield VALUE = Bitfield(0, 31);
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static constexpr Bitfield OVFL = Bitfield(31, 1);
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};
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class EeCoreCop0Register_TagLo : public SizedWordRegister
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{
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public:
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static constexpr Bitfield L = Bitfield(3, 1);
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static constexpr Bitfield R = Bitfield(4, 1);
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static constexpr Bitfield V = Bitfield(5, 1);
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static constexpr Bitfield D = Bitfield(6, 1);
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static constexpr Bitfield PTAGLO = Bitfield(12, 31);
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};
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class EeCoreCop0Register_TagHi : public SizedWordRegister
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{
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public:
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static constexpr Bitfield L = Bitfield(3, 1);
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static constexpr Bitfield R = Bitfield(4, 1);
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static constexpr Bitfield V = Bitfield(5, 1);
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static constexpr Bitfield D = Bitfield(6, 1);
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static constexpr Bitfield PTAGHI = Bitfield(12, 31);
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};
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class EeCoreCop0Register_Compare : public SizedWordRegister
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{
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public:
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EeCoreCop0Register_Compare();
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/// Writing to the Compare register causes the status.IP[7] bit
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/// to be cleared.
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void write_uword(const uword value) override;
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EeCoreCop0Register_Cause* cause;
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};
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