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Hoe Hao Cheng 2018-10-07 15:58:57 +00:00 committed by hch12907
parent 3492c0b152
commit cc9fd11233
91 changed files with 854 additions and 905 deletions
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5
README.md
View file

@ -9,8 +9,7 @@ I can only work on this in my spare time, so I am thankful for any help!
## Current status
Status as of 2018/08/06:
- Primary focus for now is on the GIF/VU's/VIF.
- Work started on the VIFs and VUs, mostly just implementing instructions left.
- Primary focus for now is on the GIF/VIF.
- Work started on the SPU2 (DMA and IOP communication done, sound generation still to be done).
- Work started on the SIO/SIO2 (controllers and MC's), IOP communication done.
- No work done yet on the IPU and GSCore.
@ -32,7 +31,7 @@ Run the following commands to invoke a build:
`cmake ..` optionally specifying `-DBOOST_ROOT={path}` depending on your environment.
`make` (or equivilant)
`make` (or equivalent)
## Running
`./orbumfront`

2
liborbum/src/Common/Constants.hpp
View file

@ -110,7 +110,7 @@ struct Constants
struct FPU
{
static constexpr int NUMBER_REGISTERS = 32;
// FPU Constants Fmax (positive) and Fmax (negative), used as the upper and lower bounds of a float value (instead of plus and minus infinity?).
static constexpr uword FMAX_POS = 0x7F7FFFFF; // Sign bit = 0 -> positive.
static constexpr uword FMAX_NEG = 0xFF7FFFFF; // Sign bit = 1 -> negative.

7
liborbum/src/Common/Types/FifoQueue/DmaFifoQueue.hpp
View file

@ -54,12 +54,11 @@ public:
return fifo_queue.has_write_available(n_bytes);
}
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(fifo_queue)
);
CEREAL_NVP(fifo_queue));
}
private:

10
liborbum/src/Common/Types/Memory/ArrayByteMemory.hpp
View file

@ -178,15 +178,15 @@ private:
bool read_only;
public:
template<class Archive>
void save(Archive & archive) const
template <class Archive>
void save(Archive& archive) const
{
archive.saveBinaryValue(memory.data(), memory.size(), "memory");
}
template<class Archive>
void load(Archive & archive)
{
template <class Archive>
void load(Archive& archive)
{
archive.loadBinaryValue(memory.data(), memory.size(), "memory");
}
};

10
liborbum/src/Common/Types/Memory/ArrayHwordMemory.hpp
View file

@ -152,15 +152,15 @@ private:
bool read_only;
public:
template<class Archive>
void save(Archive & archive) const
template <class Archive>
void save(Archive& archive) const
{
archive.saveBinaryValue(reinterpret_cast<const char*>(memory.data()), memory.size() * sizeof(uhword), "memory");
}
template<class Archive>
void load(Archive & archive)
{
template <class Archive>
void load(Archive& archive)
{
archive.loadBinaryValue(reinterpret_cast<const char*>(memory.data()), memory.size() * sizeof(uhword), "memory");
}
};

7
liborbum/src/Common/Types/Mips/BranchDelaySlot.hpp
View file

@ -81,12 +81,11 @@ protected:
uptr branch_pc;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(current_slot),
CEREAL_NVP(branch_pc)
);
CEREAL_NVP(branch_pc));
}
};

4
liborbum/src/Common/Types/Mips/MipsPipeline.hpp
View file

@ -6,7 +6,7 @@
struct MipsPipeline
{
MipsPipeline(uhword cycles = 0, uhword reg = 0) :
finish_in(cycles),
finish_in(cycles),
using_register(reg)
{
}
@ -27,7 +27,7 @@ public:
finish_in = 0;
return cycles_consumed;
}
/// Checks whether the pipeline is still running.
bool is_running() const
{

7
liborbum/src/Common/Types/Primitive.hpp
View file

@ -79,13 +79,12 @@ struct uqword
{
}
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(hi),
CEREAL_NVP(lo)
);
CEREAL_NVP(lo));
}
};

7
liborbum/src/Common/Types/Register/SizedByteRegister.hpp
View file

@ -47,11 +47,10 @@ private:
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(b)
);
CEREAL_NVP(b));
}
};

7
liborbum/src/Common/Types/Register/SizedDwordRegister.hpp
View file

@ -116,11 +116,10 @@ private:
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(d)
);
CEREAL_NVP(d));
}
};

8
liborbum/src/Common/Types/Register/SizedHwordRegister.hpp
View file

@ -2,7 +2,6 @@
#include <stdexcept>
#include <cereal/cereal.hpp>
#include "Common/Types/Primitive.hpp"
@ -73,11 +72,10 @@ private:
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(h)
);
CEREAL_NVP(h));
}
};

7
liborbum/src/Common/Types/Register/SizedQwordRegister.hpp
View file

@ -138,11 +138,10 @@ private:
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(q)
);
CEREAL_NVP(q));
}
};

7
liborbum/src/Common/Types/Register/SizedWordRegister.hpp
View file

@ -94,11 +94,10 @@ private:
bool read_only;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(w)
);
CEREAL_NVP(w));
}
};

4
liborbum/src/Controller/Ee/Timers/CEeTimers.cpp
View file

@ -58,8 +58,8 @@ void CEeTimers::tick_timer(const ControllerEvent::Type ce_type)
for (auto& unit : r.ee.timers.units)
{
auto _lock = unit.mode->scope_lock();
auto[prescale, event_type] = unit.mode->get_properties();
auto [prescale, event_type] = unit.mode->get_properties();
// Check if we need to perform reset proceedures.
if (unit.mode->write_latch)

24
liborbum/src/Controller/Ee/Vpu/Vif/CVif.cpp
View file

@ -116,7 +116,8 @@ void CVif::STCYCL(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::OFFSET(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: OFFSET") % unit->core_id);
return;
}
@ -136,7 +137,8 @@ void CVif::OFFSET(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::BASE(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: BASE") % unit->core_id);
return;
}
@ -163,7 +165,8 @@ void CVif::STMOD(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::MSKPATH3(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: MSKPATH3") % unit->core_id);
return;
}
@ -184,7 +187,8 @@ void CVif::FLUSHE(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::FLUSH(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: FLUSH") % unit->core_id);
return;
}
@ -195,7 +199,8 @@ void CVif::FLUSH(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::FLUSHA(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: FLUSHA") % unit->core_id);
return;
}
@ -214,7 +219,8 @@ void CVif::MSCNT(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::MSCALF(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: MSCALF") % unit->core_id);
return;
}
@ -241,7 +247,8 @@ void CVif::MPG(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::DIRECT(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: DIRECT") % unit->core_id);
return;
}
@ -252,7 +259,8 @@ void CVif::DIRECT(VifUnit_Base* unit, const VifcodeInstruction inst)
void CVif::DIRECTHL(VifUnit_Base* unit, const VifcodeInstruction inst)
{
// VIF1 only
if (unit->core_id != 1) {
if (unit->core_id != 1)
{
BOOST_LOG(Core::get_logger()) << str(boost::format("Warning: VIF%d called a VIF1-only instruction: DIRECTHL") % unit->core_id);
return;
}

5
liborbum/src/Controller/Ee/Vpu/Vu/CVu.cpp
View file

@ -1,9 +1,10 @@
#include <boost/format.hpp>
#include "Controller/Ee/Vpu/Vu/CVu.hpp"
#include "Resources/RResources.hpp"
CVu::CVu(Core *core) :
CVu::CVu(Core* core) :
CController(core)
{
}
@ -29,7 +30,7 @@ void CVu::handle_event(const ControllerEvent& event)
int CVu::time_to_ticks(const double time_us)
{
int ticks = static_cast<int>(time_us / 1.0e6 * Constants::EE::VPU::VU::VU_CLK_SPEED * core->get_options().system_bias_vu);
if (ticks < 10)
{
static bool warned = false;

2
liborbum/src/Controller/Ee/Vpu/Vu/CVu.hpp
View file

@ -1,8 +1,8 @@
#pragma once
#include "Core.hpp"
#include "Controller/CController.hpp"
#include "Controller/ControllerEvent.hpp"
#include "Core.hpp"
class Core;

205
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.cpp
View file

@ -1,6 +1,7 @@
#include <boost/format.hpp>
#include <variant>
#include <boost/format.hpp>
#include "Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp"
#include "Core.hpp"
@ -105,7 +106,7 @@ int CVuInterpreter::time_step(const int ticks_available)
// Register writing priority, if both upper and lower inst write to the same
// register, the priority is: COP2 Transfer > Upper Inst > Lower Inst
try
try
{
// Try obtaining the destination (will throw if the instruction writes to non-VF/VI regs)
const uword upper_dest = *decoder.upper_dest();
@ -119,7 +120,7 @@ int CVuInterpreter::time_step(const int ticks_available)
{
SizedQwordRegister original_vf = unit->vf[upper_dest];
execute_lower_instruction(unit, upper_inst, upper_info, decoder);
// The result produced by lower instruction is discarded
unit->vf[upper_dest] = original_vf;
execute_upper_instruction(unit, lower_inst, lower_info, decoder);
@ -156,83 +157,86 @@ int CVuInterpreter::execute_lower_instruction(VuUnit_Base* unit, const VuInstruc
unit->lsu.consume_cycle(1);
// If the units have finished execution, replace the original regs with new ones
if (!unit->efu.is_running()) unit->p = unit->efu.new_p;
if (!unit->fdiv.is_running()) unit->q = unit->fdiv.new_q;
if (!unit->efu.is_running())
unit->p = unit->efu.new_p;
if (!unit->fdiv.is_running())
unit->q = unit->fdiv.new_q;
// If there's a data hazard, stall
if (check_data_hazard(unit, decoder)) return 1;
if (check_data_hazard(unit, decoder))
return 1;
switch (info.pipeline)
{
case VuPipeline::EFU:
case VuPipeline::EFU:
{
if (!unit->efu.is_running())
{
if (!unit->efu.is_running())
{
// The 3 cycles: Fetch, obtain VPU register, write-back. As the
// EFU handles only the execution stage, other cycles are ignored
unit->efu = EfuPipeline(info.cpi - 3);
// The 3 cycles: Fetch, obtain VPU register, write-back. As the
// EFU handles only the execution stage, other cycles are ignored
unit->efu = EfuPipeline(info.cpi - 3);
// Store original unit->p in new_p temporarily before executing the
// instruction (since it operates on unit->p) and swap it back later.
std::swap(unit->p, unit->efu.new_p);
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
std::swap(unit->p, unit->efu.new_p);
}
break;
}
case VuPipeline::FDIV:
{
if (!unit->fdiv.is_running())
{
// The 2 cycles: Fetch, obtain VPU register. As the FDIV handles
// both execution & write-back stage, other cycles are ignored
unit->fdiv = FdivPipeline(info.cpi - 2);
// See EFU.
std::swap(unit->q, unit->fdiv.new_q);
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
std::swap(unit->q, unit->fdiv.new_q);
}
break;
}
case VuPipeline::IALU:
{
if (!unit->ialu.is_running())
{
// Try to get the destination
int dest = decoder.lower_dest().value_or(0);
// See FDIV
unit->ialu = IaluPipeline(info.cpi - 2, dest);
}
// The results are bypassed to other instructions directly, so
// there's no need to swap stuff around
// Store original unit->p in new_p temporarily before executing the
// instruction (since it operates on unit->p) and swap it back later.
std::swap(unit->p, unit->efu.new_p);
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
break;
std::swap(unit->p, unit->efu.new_p);
}
case VuPipeline::LSU:
{
if (!unit->lsu.is_running())
{
int dest = decoder.lower_dest().value_or(0);
unit->lsu = LsuPipeline(info.cpi - 2, dest);
}
break;
}
break;
}
case VuPipeline::Basic:
case VuPipeline::FDIV:
{
if (!unit->fdiv.is_running())
{
// The 2 cycles: Fetch, obtain VPU register. As the FDIV handles
// both execution & write-back stage, other cycles are ignored
unit->fdiv = FdivPipeline(info.cpi - 2);
// See EFU.
std::swap(unit->q, unit->fdiv.new_q);
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
std::swap(unit->q, unit->fdiv.new_q);
}
break;
}
case VuPipeline::IALU:
{
if (!unit->ialu.is_running())
{
// Try to get the destination
int dest = decoder.lower_dest().value_or(0);
// See FDIV
unit->ialu = IaluPipeline(info.cpi - 2, dest);
}
// The results are bypassed to other instructions directly, so
// there's no need to swap stuff around
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
break;
}
case VuPipeline::LSU:
{
if (!unit->lsu.is_running())
{
int dest = decoder.lower_dest().value_or(0);
unit->lsu = LsuPipeline(info.cpi - 2, dest);
}
break;
}
case VuPipeline::Basic:
{
(this->*VU_INSTRUCTION_TABLE[info.impl_index])(unit, inst);
}
}
return 1;
@ -246,10 +250,11 @@ int CVuInterpreter::execute_upper_instruction(VuUnit_Base* unit, VuInstruction i
}
// If there's a data hazard, stall
if (check_data_hazard(unit, decoder)) return 1;
if (check_data_hazard(unit, decoder))
return 1;
for (FmacPipeline& fmac : unit->fmac)
{
{
if (!fmac.is_running())
{
fmac = FmacPipeline(info.cpi - 2, decoder.upper_dest().value_or(0), inst.dest());
@ -266,27 +271,28 @@ bool CVuInterpreter::check_data_hazard(VuUnit_Base* unit, const VuInstructionDec
// Obtain the registers to be read by the instruction
// If the instruction does not specify the field(s), use 0 as placeholder,
// as VF0/VI0 is hardwired to 0 (and the manual did this too)
const int upper_read[3] = {
decoder.upper_src(0).value_or(0),
decoder.upper_src(1).value_or(0),
const int upper_read[3] = {
decoder.upper_src(0).value_or(0),
decoder.upper_src(1).value_or(0),
decoder.upper_src(2).value_or(-1) // this one's special because only MADD/MSUB uses this
};
const int lower_read[2] = {
decoder.lower_src(0).value_or(-1),
decoder.lower_src(1).value_or(-1)
};
const int lower_read[2] = {
decoder.lower_src(0).value_or(-1),
decoder.lower_src(1).value_or(-1)};
// If the instruction is WAITP, return true if EFU is running
if ((decoder.get_lower_inst().value) & 0x7FF == 0x7BF)
{
if (unit->efu.is_running()) return true;
if (unit->efu.is_running())
return true;
}
// If the instruction is WAITQ, return true if FDIV is running
if ((decoder.get_lower_inst().value) & 0x7FF == 0x3BF)
{
if (unit->fdiv.is_running()) return true;
if (unit->fdiv.is_running())
return true;
}
// Upper Instructions data hazard check
@ -301,16 +307,20 @@ bool CVuInterpreter::check_data_hazard(VuUnit_Base* unit, const VuInstructionDec
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(upper_read[0], inst.dest())) return true;
if (fmac.is_using_register(upper_read[1], 1 << (3 - inst.bc()))) return true;
if (fmac.is_using_register(upper_read[0], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[1], 1 << (3 - inst.bc())))
return true;
}
}
else if (decoder.decode_upper().field == VuDecodedInst::Dest)
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(upper_read[0], inst.dest())) return true;
if (fmac.is_using_register(upper_read[1], inst.dest())) return true;
if (fmac.is_using_register(upper_read[0], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[1], inst.dest()))
return true;
}
}
}
@ -320,18 +330,24 @@ bool CVuInterpreter::check_data_hazard(VuUnit_Base* unit, const VuInstructionDec
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(upper_read[0], inst.dest())) return true;
if (fmac.is_using_register(upper_read[1], inst.dest())) return true;
if (fmac.is_using_register(upper_read[2], 1 << (3 - inst.bc()))) return true;
if (fmac.is_using_register(upper_read[0], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[1], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[2], 1 << (3 - inst.bc())))
return true;
}
}
else if (decoder.decode_upper().field == VuDecodedInst::Dest)
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(upper_read[0], inst.dest())) return true;
if (fmac.is_using_register(upper_read[1], inst.dest())) return true;
if (fmac.is_using_register(upper_read[2], inst.dest())) return true;
if (fmac.is_using_register(upper_read[0], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[1], inst.dest()))
return true;
if (fmac.is_using_register(upper_read[2], inst.dest()))
return true;
}
}
}
@ -345,21 +361,26 @@ bool CVuInterpreter::check_data_hazard(VuUnit_Base* unit, const VuInstructionDec
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(lower_read[0], inst.fsf())) return true;
if (fmac.is_using_register(lower_read[1], inst.ftf())) return true;
if (fmac.is_using_register(lower_read[0], inst.fsf()))
return true;
if (fmac.is_using_register(lower_read[1], inst.ftf()))
return true;
}
}
else if (decoder.decode_lower().field == VuDecodedInst::Dest)
{
for (FmacPipeline& fmac : unit->fmac)
{
if (fmac.is_using_register(lower_read[0], inst.dest())) return true;
if (fmac.is_using_register(lower_read[1], inst.dest())) return true;
if (fmac.is_using_register(lower_read[0], inst.dest()))
return true;
if (fmac.is_using_register(lower_read[1], inst.dest()))
return true;
}
}
else if (decoder.decode_lower().field == VuDecodedInst::Int)
{
if (unit->lsu.is_using_register(lower_read[0])) return true;
if (unit->lsu.is_using_register(lower_read[0]))
return true;
}
}

333
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp
View file

@ -216,176 +216,175 @@ public:
void XITOP(VuUnit_Base* unit, const VuInstruction inst);
void (CVuInterpreter::*VU_INSTRUCTION_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTRUCTIONS])(VuUnit_Base* unit, const VuInstruction inst) =
{
&CVuInterpreter::ABS,
&CVuInterpreter::ADD,
&CVuInterpreter::ADDi,
&CVuInterpreter::ADDq,
&CVuInterpreter::ADDbc_0,
&CVuInterpreter::ADDbc_1,
&CVuInterpreter::ADDbc_2,
&CVuInterpreter::ADDbc_3,
&CVuInterpreter::ADDA,
&CVuInterpreter::ADDAi,
&CVuInterpreter::ADDAq,
&CVuInterpreter::ADDAbc_0,
&CVuInterpreter::ADDAbc_1,
&CVuInterpreter::ADDAbc_2,
&CVuInterpreter::ADDAbc_3,
&CVuInterpreter::SUB,
&CVuInterpreter::SUBi,
&CVuInterpreter::SUBq,
&CVuInterpreter::SUBbc_0,
&CVuInterpreter::SUBbc_1,
&CVuInterpreter::SUBbc_2,
&CVuInterpreter::SUBbc_3,
&CVuInterpreter::SUBA,
&CVuInterpreter::SUBAi,
&CVuInterpreter::SUBAq,
&CVuInterpreter::SUBAbc_0,
&CVuInterpreter::SUBAbc_1,
&CVuInterpreter::SUBAbc_2,
&CVuInterpreter::SUBAbc_3,
&CVuInterpreter::MUL,
&CVuInterpreter::MULi,
&CVuInterpreter::MULq,
&CVuInterpreter::MULbc_0,
&CVuInterpreter::MULbc_1,
&CVuInterpreter::MULbc_2,
&CVuInterpreter::MULbc_3,
&CVuInterpreter::MULA,
&CVuInterpreter::MULAi,
&CVuInterpreter::MULAq,
&CVuInterpreter::MULAbc_0,
&CVuInterpreter::MULAbc_1,
&CVuInterpreter::MULAbc_2,
&CVuInterpreter::MULAbc_3,
&CVuInterpreter::MADD,
&CVuInterpreter::MADDi,
&CVuInterpreter::MADDq,
&CVuInterpreter::MADDbc_0,
&CVuInterpreter::MADDbc_1,
&CVuInterpreter::MADDbc_2,
&CVuInterpreter::MADDbc_3,
&CVuInterpreter::MADDA,
&CVuInterpreter::MADDAi,
&CVuInterpreter::MADDAq,
&CVuInterpreter::MADDAbc_0,
&CVuInterpreter::MADDAbc_1,
&CVuInterpreter::MADDAbc_2,
&CVuInterpreter::MADDAbc_3,
&CVuInterpreter::MSUB,
&CVuInterpreter::MSUBi,
&CVuInterpreter::MSUBq,
&CVuInterpreter::MSUBbc_0,
&CVuInterpreter::MSUBbc_1,
&CVuInterpreter::MSUBbc_2,
&CVuInterpreter::MSUBbc_3,
&CVuInterpreter::MSUBA,
&CVuInterpreter::MSUBAi,
&CVuInterpreter::MSUBAq,
&CVuInterpreter::MSUBAbc_0,
&CVuInterpreter::MSUBAbc_1,
&CVuInterpreter::MSUBAbc_2,
&CVuInterpreter::MSUBAbc_3,
&CVuInterpreter::MAX,
&CVuInterpreter::MAXi,
&CVuInterpreter::MAXbc_0,
&CVuInterpreter::MAXbc_1,
&CVuInterpreter::MAXbc_2,
&CVuInterpreter::MAXbc_3,
&CVuInterpreter::MINI,
&CVuInterpreter::MINIi,
&CVuInterpreter::MINIbc_0,
&CVuInterpreter::MINIbc_1,
&CVuInterpreter::MINIbc_2,
&CVuInterpreter::MINIbc_3,
&CVuInterpreter::OPMULA,
&CVuInterpreter::OPMSUB,
&CVuInterpreter::NOP,
&CVuInterpreter::FTOI0,
&CVuInterpreter::FTOI4,
&CVuInterpreter::FTOI12,
&CVuInterpreter::FTOI15,
&CVuInterpreter::ITOF0,
&CVuInterpreter::ITOF4,
&CVuInterpreter::ITOF12,
&CVuInterpreter::ITOF15,
&CVuInterpreter::CLIP,
&CVuInterpreter::DIV,
&CVuInterpreter::SQRT,
&CVuInterpreter::RSQRT,
&CVuInterpreter::IADD,
&CVuInterpreter::IADDI,
&CVuInterpreter::IADDIU,
&CVuInterpreter::IAND,
&CVuInterpreter::IOR,
&CVuInterpreter::ISUB,
&CVuInterpreter::ISUBIU,
&CVuInterpreter::MOVE,
&CVuInterpreter::MFIR,
&CVuInterpreter::MTIR,
&CVuInterpreter::MR32,
&CVuInterpreter::LQ,
&CVuInterpreter::LQD,
&CVuInterpreter::LQI,
&CVuInterpreter::SQ,
&CVuInterpreter::SQD,
&CVuInterpreter::SQI,
&CVuInterpreter::ILW,
&CVuInterpreter::ISW,
&CVuInterpreter::ILWR,
&CVuInterpreter::ISWR,
&CVuInterpreter::RINIT,
&CVuInterpreter::RGET,
&CVuInterpreter::RNEXT,
&CVuInterpreter::RXOR,
&CVuInterpreter::WAITQ,
&CVuInterpreter::FSAND,
&CVuInterpreter::FSEQ,
&CVuInterpreter::FSOR,
&CVuInterpreter::FSSET,
&CVuInterpreter::FMAND,
&CVuInterpreter::FMEQ,
&CVuInterpreter::FMOR,
&CVuInterpreter::FCAND,
&CVuInterpreter::FCEQ,
&CVuInterpreter::FCOR,
&CVuInterpreter::FCSET,
&CVuInterpreter::FCGET,
&CVuInterpreter::IBEQ,
&CVuInterpreter::IBGEZ,
&CVuInterpreter::IBGTZ,
&CVuInterpreter::IBLEZ,
&CVuInterpreter::IBLTZ,
&CVuInterpreter::IBNE,
&CVuInterpreter::B,
&CVuInterpreter::BAL,
&CVuInterpreter::JR,
&CVuInterpreter::JALR,
&CVuInterpreter::MFP,
&CVuInterpreter::WAITP,
&CVuInterpreter::ESADD,
&CVuInterpreter::ERSADD,
&CVuInterpreter::ELENG,
&CVuInterpreter::ERLENG,
&CVuInterpreter::EATANxy,
&CVuInterpreter::EATANxz,
&CVuInterpreter::ESUM,
&CVuInterpreter::ERCPR,
&CVuInterpreter::ESQRT,
&CVuInterpreter::ERSQRT,
&CVuInterpreter::ESIN,
&CVuInterpreter::EATAN,
&CVuInterpreter::EEXP,
&CVuInterpreter::XGKICK,
&CVuInterpreter::XTOP,
&CVuInterpreter::XITOP
};
{
&CVuInterpreter::ABS,
&CVuInterpreter::ADD,
&CVuInterpreter::ADDi,
&CVuInterpreter::ADDq,
&CVuInterpreter::ADDbc_0,
&CVuInterpreter::ADDbc_1,
&CVuInterpreter::ADDbc_2,
&CVuInterpreter::ADDbc_3,
&CVuInterpreter::ADDA,
&CVuInterpreter::ADDAi,
&CVuInterpreter::ADDAq,
&CVuInterpreter::ADDAbc_0,
&CVuInterpreter::ADDAbc_1,
&CVuInterpreter::ADDAbc_2,
&CVuInterpreter::ADDAbc_3,
&CVuInterpreter::SUB,
&CVuInterpreter::SUBi,
&CVuInterpreter::SUBq,
&CVuInterpreter::SUBbc_0,
&CVuInterpreter::SUBbc_1,
&CVuInterpreter::SUBbc_2,
&CVuInterpreter::SUBbc_3,
&CVuInterpreter::SUBA,
&CVuInterpreter::SUBAi,
&CVuInterpreter::SUBAq,
&CVuInterpreter::SUBAbc_0,
&CVuInterpreter::SUBAbc_1,
&CVuInterpreter::SUBAbc_2,
&CVuInterpreter::SUBAbc_3,
&CVuInterpreter::MUL,
&CVuInterpreter::MULi,
&CVuInterpreter::MULq,
&CVuInterpreter::MULbc_0,
&CVuInterpreter::MULbc_1,
&CVuInterpreter::MULbc_2,
&CVuInterpreter::MULbc_3,
&CVuInterpreter::MULA,
&CVuInterpreter::MULAi,
&CVuInterpreter::MULAq,
&CVuInterpreter::MULAbc_0,
&CVuInterpreter::MULAbc_1,
&CVuInterpreter::MULAbc_2,
&CVuInterpreter::MULAbc_3,
&CVuInterpreter::MADD,
&CVuInterpreter::MADDi,
&CVuInterpreter::MADDq,
&CVuInterpreter::MADDbc_0,
&CVuInterpreter::MADDbc_1,
&CVuInterpreter::MADDbc_2,
&CVuInterpreter::MADDbc_3,
&CVuInterpreter::MADDA,
&CVuInterpreter::MADDAi,
&CVuInterpreter::MADDAq,
&CVuInterpreter::MADDAbc_0,
&CVuInterpreter::MADDAbc_1,
&CVuInterpreter::MADDAbc_2,
&CVuInterpreter::MADDAbc_3,
&CVuInterpreter::MSUB,
&CVuInterpreter::MSUBi,
&CVuInterpreter::MSUBq,
&CVuInterpreter::MSUBbc_0,
&CVuInterpreter::MSUBbc_1,
&CVuInterpreter::MSUBbc_2,
&CVuInterpreter::MSUBbc_3,
&CVuInterpreter::MSUBA,
&CVuInterpreter::MSUBAi,
&CVuInterpreter::MSUBAq,
&CVuInterpreter::MSUBAbc_0,
&CVuInterpreter::MSUBAbc_1,
&CVuInterpreter::MSUBAbc_2,
&CVuInterpreter::MSUBAbc_3,
&CVuInterpreter::MAX,
&CVuInterpreter::MAXi,
&CVuInterpreter::MAXbc_0,
&CVuInterpreter::MAXbc_1,
&CVuInterpreter::MAXbc_2,
&CVuInterpreter::MAXbc_3,
&CVuInterpreter::MINI,
&CVuInterpreter::MINIi,
&CVuInterpreter::MINIbc_0,
&CVuInterpreter::MINIbc_1,
&CVuInterpreter::MINIbc_2,
&CVuInterpreter::MINIbc_3,
&CVuInterpreter::OPMULA,
&CVuInterpreter::OPMSUB,
&CVuInterpreter::NOP,
&CVuInterpreter::FTOI0,
&CVuInterpreter::FTOI4,
&CVuInterpreter::FTOI12,
&CVuInterpreter::FTOI15,
&CVuInterpreter::ITOF0,
&CVuInterpreter::ITOF4,
&CVuInterpreter::ITOF12,
&CVuInterpreter::ITOF15,
&CVuInterpreter::CLIP,
&CVuInterpreter::DIV,
&CVuInterpreter::SQRT,
&CVuInterpreter::RSQRT,
&CVuInterpreter::IADD,
&CVuInterpreter::IADDI,
&CVuInterpreter::IADDIU,
&CVuInterpreter::IAND,
&CVuInterpreter::IOR,
&CVuInterpreter::ISUB,
&CVuInterpreter::ISUBIU,
&CVuInterpreter::MOVE,
&CVuInterpreter::MFIR,
&CVuInterpreter::MTIR,
&CVuInterpreter::MR32,
&CVuInterpreter::LQ,
&CVuInterpreter::LQD,
&CVuInterpreter::LQI,
&CVuInterpreter::SQ,
&CVuInterpreter::SQD,
&CVuInterpreter::SQI,
&CVuInterpreter::ILW,
&CVuInterpreter::ISW,
&CVuInterpreter::ILWR,
&CVuInterpreter::ISWR,
&CVuInterpreter::RINIT,
&CVuInterpreter::RGET,
&CVuInterpreter::RNEXT,
&CVuInterpreter::RXOR,
&CVuInterpreter::WAITQ,
&CVuInterpreter::FSAND,
&CVuInterpreter::FSEQ,
&CVuInterpreter::FSOR,
&CVuInterpreter::FSSET,
&CVuInterpreter::FMAND,
&CVuInterpreter::FMEQ,
&CVuInterpreter::FMOR,
&CVuInterpreter::FCAND,
&CVuInterpreter::FCEQ,
&CVuInterpreter::FCOR,
&CVuInterpreter::FCSET,
&CVuInterpreter::FCGET,
&CVuInterpreter::IBEQ,
&CVuInterpreter::IBGEZ,
&CVuInterpreter::IBGTZ,
&CVuInterpreter::IBLEZ,
&CVuInterpreter::IBLTZ,
&CVuInterpreter::IBNE,
&CVuInterpreter::B,
&CVuInterpreter::BAL,
&CVuInterpreter::JR,
&CVuInterpreter::JALR,
&CVuInterpreter::MFP,
&CVuInterpreter::WAITP,
&CVuInterpreter::ESADD,
&CVuInterpreter::ERSADD,
&CVuInterpreter::ELENG,
&CVuInterpreter::ERLENG,
&CVuInterpreter::EATANxy,
&CVuInterpreter::EATANxz,
&CVuInterpreter::ESUM,
&CVuInterpreter::ERCPR,
&CVuInterpreter::ESQRT,
&CVuInterpreter::ERSQRT,
&CVuInterpreter::ESIN,
&CVuInterpreter::EATAN,
&CVuInterpreter::EEXP,
&CVuInterpreter::XGKICK,
&CVuInterpreter::XTOP,
&CVuInterpreter::XITOP};
private:
bool check_data_hazard(VuUnit_Base* unit, const VuInstructionDecoder& decoder) const;
int execute_upper_instruction(VuUnit_Base* unit, VuInstruction inst, MipsInstructionInfo info, const VuInstructionDecoder& decoder);
int execute_lower_instruction(VuUnit_Base* unit, VuInstruction inst, MipsInstructionInfo info, const VuInstructionDecoder& decoder);
};

6
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter_CONVERT.cpp
View file

@ -3,7 +3,7 @@
#include "Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp"
#include "Core.hpp"
// All instructions here are related to the conversion between floating-points and
// All instructions here are related to the conversion between floating-points and
// fixed-points.
//
// FTOIx are the instructions for converting a float to a fixed with (32-x) bits
@ -45,7 +45,7 @@ void CVuInterpreter::FTOI4(VuUnit_Base* unit, const VuInstruction inst)
// Cast the resultant float into an integer
const uword result = static_cast<uword>(f);
ft.write_uword(field, result);
}
}
@ -100,7 +100,7 @@ void CVuInterpreter::ITOF0(VuUnit_Base* unit, const VuInstruction inst)
if (inst.test_dest_field(field))
{
uword u = fs.read_uword(field);
// No fractional parts to worry about, just cast it
const f32 result = static_cast<f32>(u);

3
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter_EFU.cpp
View file

@ -1,6 +1,7 @@
#include <boost/format.hpp>
#include <cmath>
#include <boost/format.hpp>
#include "Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp"
#include "Core.hpp"

82
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter_FLOAT.cpp
View file

@ -9,7 +9,7 @@
#include "Utilities/Utilities.hpp"
// All instructions here are related to float arithmetic.
//
//
// Explaination for the comments:
// VF[x] - the x-th register of VF
// VF[x](f) - the f field of the x-th register of VF, if not specified
@ -621,7 +621,7 @@ void CVuInterpreter::MULq(VuUnit_Base* unit, const VuInstruction inst)
SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
SizedWordRegister& reg_source_2 = unit->q;
SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
SizedQwordRegister& reg_dest = unit->vf[inst.fd()];
FpuFlags flags;
for (auto field : VuVectorField::VECTOR_FIELDS)
@ -876,13 +876,13 @@ void CVuInterpreter::MADDi(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -909,13 +909,13 @@ void CVuInterpreter::MADDq(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -944,13 +944,13 @@ void CVuInterpreter::MADDbc(VuUnit_Base* unit, const VuInstruction inst, const i
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(bc);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1001,13 +1001,13 @@ void CVuInterpreter::MADDA(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(field);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1034,13 +1034,13 @@ void CVuInterpreter::MADDAi(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1067,13 +1067,13 @@ void CVuInterpreter::MADDAq(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1102,13 +1102,13 @@ void CVuInterpreter::MADDAbc(VuUnit_Base* unit, const VuInstruction inst, const
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(bc);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c + multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1159,13 +1159,13 @@ void CVuInterpreter::MSUB(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(field);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1192,13 +1192,13 @@ void CVuInterpreter::MSUBi(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1225,13 +1225,13 @@ void CVuInterpreter::MSUBq(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1260,13 +1260,13 @@ void CVuInterpreter::MSUBbc(VuUnit_Base* unit, const VuInstruction inst, const i
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(bc);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1317,13 +1317,13 @@ void CVuInterpreter::MSUBA(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(field);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1350,13 +1350,13 @@ void CVuInterpreter::MSUBAi(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1383,13 +1383,13 @@ void CVuInterpreter::MSUBAq(VuUnit_Base* unit, const VuInstruction inst)
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float();
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1418,13 +1418,13 @@ void CVuInterpreter::MSUBAbc(VuUnit_Base* unit, const VuInstruction inst, const
const f32 a = reg_source_1.read_float(field);
const f32 b = reg_source_2.read_float(bc);
const f32 c = reg_source_3.read_float(field);
const f32 multiplied = to_ps2_float(a * b, flags); // See MADD for details
unit->mac.update_vector_field(field, flags);
const f32 result = to_ps2_float(c - multiplied, flags);
unit->mac.update_vector_field(field, flags);
reg_dest.write_float(field, result);
}
else
@ -1699,24 +1699,24 @@ void CVuInterpreter::OPMSUB(VuUnit_Base* unit, const VuInstruction inst)
void CVuInterpreter::DIV(VuUnit_Base* unit, const VuInstruction inst)
{
// Q = vf[fs] / vs[ft]
SizedWordRegister& q = unit->q;
SizedQwordRegister& fs = unit->vf[inst.fs()];
SizedQwordRegister& ft = unit->vf[inst.ft()];
FpuFlags flags;
const f32 result = to_ps2_float(fs.read_float(inst.fsf()) / ft.read_float(inst.ftf()), flags);
// If ft[ftf] is 0, division by zero occurs...
if (ft.read_float(inst.ftf()) == 0.0f)
if (ft.read_float(inst.ftf()) == 0.0f)
{
// ...and if the dividend is 0, set the I flag, otherwise the D flag
// See VU Users Manual pg 40
if (fs.read_float(inst.fsf()) == 0.0f)
if (fs.read_float(inst.fsf()) == 0.0f)
{
unit->status.set_i_flag_sticky(1);
}
else
}
else
{
unit->status.set_d_flag_sticky(1);
}
@ -1735,7 +1735,7 @@ void CVuInterpreter::SQRT(VuUnit_Base* unit, const VuInstruction inst)
const f32 result = std::sqrt(std::abs(ft.read_float(inst.ftf())));
// If the float is negative, set the I flag
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
{
unit->status.set_i_flag_sticky(1);
}
@ -1756,13 +1756,13 @@ void CVuInterpreter::RSQRT(VuUnit_Base* unit, const VuInstruction inst)
const f32 result = std::sqrt(std::abs(ft.read_float(inst.ftf())));
// Set the I flag if the number to be sqrt-ed is negative.
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
if ((ft.read_uword(inst.ftf()) >> 31 & 1) == 1)
{
unit->status.set_i_flag_sticky(1);
}
// Set the D flag if the final result is 1 / 0
if (ft.read_float(inst.ftf()) == 0.0f)
if (ft.read_float(inst.ftf()) == 0.0f)
{
unit->status.set_d_flag_sticky(1);
}

31
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter_OTHER.cpp
View file

@ -1,6 +1,7 @@
#include <boost/format.hpp>
#include <cmath>
#include <boost/format.hpp>
#include "Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter.hpp"
#include "Core.hpp"
#include "Resources/RResources.hpp"
@ -30,11 +31,11 @@ void CVuInterpreter::CLIP(VuUnit_Base* unit, const VuInstruction inst)
const f32 ft = std::abs(reg_source_2.read_float(VuVectorField::W));
clip.shift_judgement();
clip.insert_field(VuUnitRegister_Clipping::POSX_0, reg_source_1.read_float(VuVectorField::X) > ft);
clip.insert_field(VuUnitRegister_Clipping::POSX_0, reg_source_1.read_float(VuVectorField::X) > ft);
clip.insert_field(VuUnitRegister_Clipping::NEGX_0, reg_source_1.read_float(VuVectorField::X) < -ft);
clip.insert_field(VuUnitRegister_Clipping::POSY_0, reg_source_1.read_float(VuVectorField::Y) > ft);
clip.insert_field(VuUnitRegister_Clipping::POSY_0, reg_source_1.read_float(VuVectorField::Y) > ft);
clip.insert_field(VuUnitRegister_Clipping::NEGY_0, reg_source_1.read_float(VuVectorField::Y) < -ft);
clip.insert_field(VuUnitRegister_Clipping::POSZ_0, reg_source_1.read_float(VuVectorField::Z) > ft);
clip.insert_field(VuUnitRegister_Clipping::POSZ_0, reg_source_1.read_float(VuVectorField::Z) > ft);
clip.insert_field(VuUnitRegister_Clipping::NEGZ_0, reg_source_1.read_float(VuVectorField::Z) < -ft);
}
@ -42,7 +43,7 @@ void CVuInterpreter::RINIT(VuUnit_Base* unit, const VuInstruction inst)
{
SizedQwordRegister& reg_source = unit->vf[inst.fs()];
SizedWordRegister& reg_dest = unit->r;
// Writes a float consisting 23 bits of R as mantissa and 001111111 as exp+sign.
constexpr uword append = 0b001111111 << 23;
const uword fsf = (reg_source.read_uword(inst.fsf()) & 0x7FFFFF) | append;
@ -54,9 +55,9 @@ void CVuInterpreter::RGET(VuUnit_Base* unit, const VuInstruction inst)
SizedWordRegister& reg_source = unit->r;
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
reg_dest.write_uword(field, reg_source.read_uword());
}
@ -72,7 +73,7 @@ void CVuInterpreter::RNEXT(VuUnit_Base* unit, const VuInstruction inst)
const int x = (reg_R.read_uword() >> 4) & 1;
const int y = (reg_R.read_uword() >> 22) & 1;
reg_R.write_uword(((reg_R.read_uword() << 1) ^ (x ^ y)) & 0x7FFFFF);
// Append the exp+sign to R
reg_R.write_uword(reg_R.read_uword() | 0b001111111 << 23);
}
@ -106,7 +107,7 @@ void CVuInterpreter::IBEQ(VuUnit_Base* unit, const VuInstruction inst)
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
if (reg_source_1.read_uhword() == reg_source_2.read_uhword())
if (reg_source_1.read_uhword() == reg_source_2.read_uhword())
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -117,7 +118,7 @@ void CVuInterpreter::IBGEZ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
if (reg_source_1.read_uhword() >= 0)
if (reg_source_1.read_uhword() >= 0)
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -128,7 +129,7 @@ void CVuInterpreter::IBGTZ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
if (reg_source_1.read_uhword() > 0)
if (reg_source_1.read_uhword() > 0)
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -139,7 +140,7 @@ void CVuInterpreter::IBLEZ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
if (reg_source_1.read_uhword() <= 0)
if (reg_source_1.read_uhword() <= 0)
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -150,7 +151,7 @@ void CVuInterpreter::IBLTZ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
if (reg_source_1.read_uhword() < 0)
if (reg_source_1.read_uhword() < 0)
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -162,7 +163,7 @@ void CVuInterpreter::IBNE(VuUnit_Base* unit, const VuInstruction inst)
SizedHwordRegister& reg_source_1 = unit->vi[inst.is()];
SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
if (reg_source_1.read_uhword() != reg_source_2.read_uhword())
if (reg_source_1.read_uhword() != reg_source_2.read_uhword())
{
shword offset_by = extend_integer<shword, uhword, 11>(inst.imm11());
unit->bdelay.set_branch_itype(unit->pc, offset_by);
@ -262,6 +263,6 @@ void CVuInterpreter::XITOP(VuUnit_Base* unit, const VuInstruction inst)
const RResources& r = core->get_resources();
VifUnit_Base* vif = r.ee.vpu.vif.units[unit->core_id];
reg_dest.write_uhword(vif->itop.read_uword());
}

55
liborbum/src/Controller/Ee/Vpu/Vu/Interpreter/CVuInterpreter_TRANSFER.cpp
View file

@ -13,9 +13,9 @@ void CVuInterpreter::MOVE(VuUnit_Base* unit, const VuInstruction inst)
SizedQwordRegister& reg_source = unit->vf[inst.fs()];
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
reg_dest.write_uword(reg_source.read_uword(field), field);
}
@ -27,9 +27,9 @@ void CVuInterpreter::MFIR(VuUnit_Base* unit, const VuInstruction inst)
SizedHwordRegister& reg_source = unit->vi[inst.is()];
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
reg_dest.write_uword(reg_source.read_uhword(), field);
}
@ -59,14 +59,14 @@ void CVuInterpreter::LQ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source = unit->vi[inst.is()];
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
const shword offset = extend_integer<uhword, shword, 11>(inst.imm11());
const uword address = (offset + reg_source.read_uhword()) * NUMBER_BYTES_IN_QWORD;
const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
// Investigate?: Endianness scares me
reg_dest.write_uword(field, source.uw[field]);
@ -78,16 +78,16 @@ void CVuInterpreter::LQD(VuUnit_Base* unit, const VuInstruction inst)
{
SizedHwordRegister& reg_source = unit->vi[inst.is()];
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
// Pre-decrement VI first
reg_source.write_uhword(reg_source.read_uhword() - 1);
const uword address = reg_source.read_uhword() * NUMBER_BYTES_IN_QWORD;
const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
// Investigate?: Endianness scares me
reg_dest.write_uword(field, source.uw[field]);
@ -103,9 +103,9 @@ void CVuInterpreter::LQI(VuUnit_Base* unit, const VuInstruction inst)
const uword address = reg_source.read_uhword() * NUMBER_BYTES_IN_QWORD;
const uqword source = unit->bus.read_uqword(BusContext::Vu, address);
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
// Investigate?: Endianness scares me
reg_dest.write_uword(field, source.uw[field]);
@ -120,15 +120,15 @@ void CVuInterpreter::SQ(VuUnit_Base* unit, const VuInstruction inst)
{
SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
const shword offset = extend_integer<uhword, shword, 11>(inst.imm11());
const uword address = (offset + reg_source_2.read_uhword()) * NUMBER_BYTES_IN_QWORD;
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
}
}
}
@ -137,16 +137,16 @@ void CVuInterpreter::SQD(VuUnit_Base* unit, const VuInstruction inst)
{
SizedQwordRegister& reg_source_1 = unit->vf[inst.fs()];
SizedHwordRegister& reg_source_2 = unit->vi[inst.it()];
reg_source_2.write_uhword(reg_source_2.read_uhword() - 1);
const uword address = reg_source_2.read_uhword() * NUMBER_BYTES_IN_QWORD;
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
}
}
}
@ -164,7 +164,7 @@ void CVuInterpreter::SQI(VuUnit_Base* unit, const VuInstruction inst)
{
if (inst.test_dest_field(field))
{
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uword(field));
}
}
@ -188,7 +188,7 @@ void CVuInterpreter::ILW(VuUnit_Base* unit, const VuInstruction inst)
const uword source = unit->bus.read_uqword(BusContext::Vu, address).uw[field];
reg_dest.write_uhword(static_cast<uhword>(source));
}
}
}
}
void CVuInterpreter::ISW(VuUnit_Base* unit, const VuInstruction inst)
@ -203,7 +203,7 @@ void CVuInterpreter::ISW(VuUnit_Base* unit, const VuInstruction inst)
{
if (inst.test_dest_field(field))
{
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
}
}
}
@ -239,7 +239,7 @@ void CVuInterpreter::ISWR(VuUnit_Base* unit, const VuInstruction inst)
{
if (inst.test_dest_field(field))
{
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
unit->bus.write_uword(BusContext::Vu, address + NUMBER_BYTES_IN_WORD * field, reg_source_1.read_uhword());
}
}
}
@ -251,8 +251,7 @@ void CVuInterpreter::LOI(VuUnit_Base* unit, const VuInstruction inst)
unit->i.write_uword(inst.value);
// (In case you are wondering... LOI is a pseudo-instruction, it's
// (In case you are wondering... LOI is a pseudo-instruction, it's
// not supposed to be referenced)
}
@ -261,9 +260,9 @@ void CVuInterpreter::MFP(VuUnit_Base* unit, const VuInstruction inst)
SizedWordRegister& reg_source = unit->p;
SizedQwordRegister& reg_dest = unit->vf[inst.ft()];
for (auto field : VuVectorField::VECTOR_FIELDS)
for (auto field : VuVectorField::VECTOR_FIELDS)
{
if (inst.test_dest_field(field))
if (inst.test_dest_field(field))
{
reg_dest.write_uword(reg_source.read_uword(), field);
}

2
liborbum/src/Controller/Iop/Timers/CIopTimers.cpp
View file

@ -58,7 +58,7 @@ void CIopTimers::tick_timer(const ControllerEvent::Type ce_type)
{
auto _lock = unit->mode.scope_lock();
auto[prescale, event_type] = unit->mode.get_properties(unit->unit_id);
auto [prescale, event_type] = unit->mode.get_properties(unit->unit_id);
// Check if we need to perform reset proceedures.
if (unit->mode.write_latch)

6
liborbum/src/Core.cpp
View file

@ -12,8 +12,8 @@
#include <boost/log/utility/setup/file.hpp>
#include <Console.hpp>
#include <Macros.hpp>
#include <Datetime.hpp>
#include <Macros.hpp>
#include "Core.hpp"
@ -238,7 +238,7 @@ void Core::init_logging()
const std::string logs_dir_path = options.logs_dir_path;
boost::filesystem::create_directory(logs_dir_path);
boost::log::add_common_attributes();
boost::log::add_file_log(
boost::log::keywords::file_name = logs_dir_path + "log_" + datetime_fmt(Core::DATETIME_FORMAT) + ".log",
boost::log::keywords::format = "[%TimeStamp%]: %Message%");
@ -247,7 +247,7 @@ void Core::init_logging()
boost::log::keywords::format = "[%TimeStamp%]: %Message%");
}
void Core::save_state()
void Core::save_state()
{
const std::string save_states_dir_path = options.save_states_dir_path;
boost::filesystem::create_directory(save_states_dir_path);

6
liborbum/src/Core.hpp
View file

@ -96,8 +96,8 @@ private:
class Core
{
public:
static constexpr const char * DATETIME_FORMAT = "%Y-%m-%d_%H-%M-%S";
static constexpr const char* DATETIME_FORMAT = "%Y-%m-%d_%H-%M-%S";
Core(const CoreOptions& options);
~Core();
@ -166,6 +166,6 @@ public:
/// Save the current emulator state. JSON is used for debugging purposes
/// (makes it easy to view state).
/// TODO: for debugging only for now - some things are not serialized,
/// but most of the important stuff is.
/// but most of the important stuff is.
void save_state();
};

7
liborbum/src/Resources/Cdvd/CdvdNvrams.hpp
View file

@ -87,16 +87,15 @@ protected:
int access_block_index;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(memory),
CEREAL_NVP(access_read_write),
CEREAL_NVP(access_area_index),
CEREAL_NVP(access_max_block_index),
CEREAL_NVP(access_block_index)
);
CEREAL_NVP(access_block_index));
}
};

14
liborbum/src/Resources/Cdvd/CdvdRegisters.hpp
View file

@ -32,13 +32,12 @@ public:
DmaFifoQueue<> data_in;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ready),
CEREAL_NVP(data_in)
);
CEREAL_NVP(data_in));
}
};
@ -64,12 +63,11 @@ public:
CdvdRegister_Ns_Rdy_Din* ns_rdy_din;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedByteRegister>(this),
CEREAL_NVP(write_latch)
);
CEREAL_NVP(write_latch));
}
};

7
liborbum/src/Resources/Cdvd/CdvdRtc.hpp
View file

@ -27,8 +27,8 @@ private:
double microseconds;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(second),
@ -37,7 +37,6 @@ public:
CEREAL_NVP(day),
CEREAL_NVP(month),
CEREAL_NVP(year),
CEREAL_NVP(microseconds)
);
CEREAL_NVP(microseconds));
}
};

7
liborbum/src/Resources/Cdvd/RCdvd.hpp
View file

@ -68,8 +68,8 @@ public:
CdvdRtc rtc;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(n_command),
@ -107,7 +107,6 @@ public:
CEREAL_NVP(key_xor),
CEREAL_NVP(dec_set),
CEREAL_NVP(nvram),
CEREAL_NVP(rtc)
);
CEREAL_NVP(rtc));
}
};

7
liborbum/src/Resources/Ee/Core/EeCoreCop0.hpp
View file

@ -77,8 +77,8 @@ public:
SizedWordRegister* pcr_registers[Constants::EE::EECore::COP0::NUMBER_PCR_REGISTERS];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(index),
@ -120,7 +120,6 @@ public:
CEREAL_NVP(dvbm),
CEREAL_NVP(pccr),
CEREAL_NVP(pcr0),
CEREAL_NVP(pcr1)
);
CEREAL_NVP(pcr1));
}
};

14
liborbum/src/Resources/Ee/Core/EeCoreCop0Registers.hpp
View file

@ -120,15 +120,14 @@ private:
void handle_count_interrupt_state_update();
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(interrupts_masked),
CEREAL_NVP(operating_context),
CEREAL_NVP(count_interrupts_enabled)
);
CEREAL_NVP(count_interrupts_enabled));
}
};
@ -166,13 +165,12 @@ private:
bool irq_lines[8];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(irq_lines)
);
CEREAL_NVP(irq_lines));
}
};

7
liborbum/src/Resources/Ee/Core/EeCoreFpu.hpp
View file

@ -40,14 +40,13 @@ public:
EeCoreCop0* cop0;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(fpr),
CEREAL_NVP(acc),
CEREAL_NVP(irr),
CEREAL_NVP(csr)
);
CEREAL_NVP(csr));
}
};

7
liborbum/src/Resources/Ee/Core/EeCoreR5900.hpp
View file

@ -41,8 +41,8 @@ public:
SizedWordRegister sa;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pc),
@ -50,7 +50,6 @@ public:
CEREAL_NVP(gpr),
CEREAL_NVP(hi),
CEREAL_NVP(lo),
CEREAL_NVP(sa)
);
CEREAL_NVP(sa));
}
};

7
liborbum/src/Resources/Ee/Core/EeCoreTlb.hpp
View file

@ -43,11 +43,10 @@ private:
bool is_match(const uptr vaddress, const int index) const;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(tlb_entries)
);
CEREAL_NVP(tlb_entries));
}
};

21
liborbum/src/Resources/Ee/Core/EeCoreTlbEntry.hpp
View file

@ -49,14 +49,13 @@ public:
uword tlb_mask;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pagemask),
CEREAL_NVP(evenodd_mask),
CEREAL_NVP(tlb_mask)
);
CEREAL_NVP(tlb_mask));
}
};
@ -82,21 +81,20 @@ public:
bool d;
bool v;
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pfn),
CEREAL_NVP(c),
CEREAL_NVP(d),
CEREAL_NVP(v)
);
CEREAL_NVP(v));
}
} physical_info[2]; // Index 0 = Even, index 1 = Odd.
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(mask),
@ -104,7 +102,6 @@ public:
CEREAL_NVP(g),
CEREAL_NVP(asid),
CEREAL_NVP(s),
CEREAL_NVP(physical_info)
);
CEREAL_NVP(physical_info));
}
};

7
liborbum/src/Resources/Ee/Core/REeCore.hpp
View file

@ -32,15 +32,14 @@ public:
ArrayByteMemory scratchpad_memory;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(r5900),
CEREAL_NVP(cop0),
CEREAL_NVP(fpu),
CEREAL_NVP(tlb),
CEREAL_NVP(scratchpad_memory)
);
CEREAL_NVP(scratchpad_memory));
}
};

7
liborbum/src/Resources/Ee/Dmac/EeDmacChannelRegisters.hpp
View file

@ -73,8 +73,8 @@ public:
EeDmatag dma_tag;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
@ -82,8 +82,7 @@ public:
CEREAL_NVP(tag_exit),
CEREAL_NVP(tag_stall),
CEREAL_NVP(tag_irq),
CEREAL_NVP(dma_tag)
);
CEREAL_NVP(dma_tag));
}
};

35
liborbum/src/Resources/Ee/Dmac/EeDmacChannels.hpp
View file

@ -51,15 +51,14 @@ public:
EeDmacChannelRegister_Chcr_Ty chcr;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(channel_id),
CEREAL_NVP(madr),
CEREAL_NVP(qwc),
CEREAL_NVP(chcr)
);
CEREAL_NVP(chcr));
}
};
@ -76,13 +75,12 @@ public:
EeDmacChannelRegister_Addr tadr;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(tadr)
);
CEREAL_NVP(tadr));
}
};
@ -99,13 +97,12 @@ public:
EeDmacChannelRegister_Addr asr[2];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<EeDmacChannel_Tadr<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(asr)
);
CEREAL_NVP(asr));
}
};
@ -122,13 +119,12 @@ public:
SizedWordRegister sadr;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(sadr)
);
CEREAL_NVP(sadr));
}
};
@ -146,13 +142,12 @@ public:
SizedWordRegister sadr;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<EeDmacChannel_Base<EeDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(tadr),
CEREAL_NVP(sadr)
);
CEREAL_NVP(sadr));
}
};

7
liborbum/src/Resources/Ee/Dmac/EeDmatag.hpp
View file

@ -79,12 +79,11 @@ public:
uword tag1;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(tag0),
CEREAL_NVP(tag1)
);
CEREAL_NVP(tag1));
}
};

7
liborbum/src/Resources/Ee/Dmac/REeDmac.hpp
View file

@ -60,8 +60,8 @@ public:
ArrayByteMemory memory_f5a0;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(channel_vif0),
@ -98,7 +98,6 @@ public:
CEREAL_NVP(memory_e070),
CEREAL_NVP(memory_f500),
CEREAL_NVP(memory_f530),
CEREAL_NVP(memory_f5a0)
);
CEREAL_NVP(memory_f5a0));
}
};

16
liborbum/src/Resources/Ee/EeRegisters.hpp
View file

@ -1,7 +1,7 @@
#pragma once
#include <cereal/cereal.hpp>
#include <cereal/access.hpp>
#include <cereal/cereal.hpp>
#include <cereal/types/polymorphic.hpp>
#include <cereal/types/string.hpp>
@ -39,13 +39,14 @@ private:
#endif
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<ArrayByteMemory>(this)
#if DEBUG_LOG_SIO_MESSAGES
,CEREAL_NVP(sio_buffer)
,
CEREAL_NVP(sio_buffer)
#endif
);
}
@ -74,13 +75,12 @@ private:
static constexpr int rdram_devices = 2; // Put 8 for TOOL and 2 for PS2 and PSX.
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<ArrayByteMemory>(this),
CEREAL_NVP(rdram_sdevid)
);
CEREAL_NVP(rdram_sdevid));
}
};

7
liborbum/src/Resources/Ee/Gif/RGif.hpp
View file

@ -25,8 +25,8 @@ public:
ArrayByteMemory memory_30b0;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ctrl),
@ -40,7 +40,6 @@ public:
CEREAL_NVP(cnt),
CEREAL_NVP(p3cnt),
CEREAL_NVP(p3tag),
CEREAL_NVP(memory_30b0)
);
CEREAL_NVP(memory_30b0));
}
};

7
liborbum/src/Resources/Ee/Intc/REeIntc.hpp
View file

@ -16,13 +16,12 @@ public:
ArrayByteMemory memory_f020;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(mask),
CEREAL_NVP(stat),
CEREAL_NVP(memory_f020)
);
CEREAL_NVP(memory_f020));
}
};

7
liborbum/src/Resources/Ee/Ipu/RIpu.hpp
View file

@ -21,15 +21,14 @@ public:
ArrayByteMemory memory_2040;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(cmd),
CEREAL_NVP(ctrl),
CEREAL_NVP(bp),
CEREAL_NVP(top),
CEREAL_NVP(memory_2040)
);
CEREAL_NVP(memory_2040));
}
};

7
liborbum/src/Resources/Ee/REe.hpp
View file

@ -60,8 +60,8 @@ public:
ArrayByteMemory memory_f450;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(core),
@ -78,7 +78,6 @@ public:
CEREAL_NVP(memory_f410),
CEREAL_NVP(register_f420),
CEREAL_NVP(memory_mch),
CEREAL_NVP(memory_f450)
);
CEREAL_NVP(memory_f450));
}
};

14
liborbum/src/Resources/Ee/Timers/EeTimersUnitRegisters.hpp
View file

@ -37,15 +37,14 @@ private:
int prescale_count;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(is_overflowed),
CEREAL_NVP(prescale_target),
CEREAL_NVP(prescale_count)
);
CEREAL_NVP(prescale_count));
}
};
@ -84,12 +83,11 @@ public:
std::pair<uword, ControllerEventType> get_properties();
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(write_latch)
);
CEREAL_NVP(write_latch));
}
};

14
liborbum/src/Resources/Ee/Timers/EeTimersUnits.hpp
View file

@ -34,14 +34,13 @@ public:
SizedWordRegister compare;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(count),
CEREAL_NVP(mode),
CEREAL_NVP(compare)
);
CEREAL_NVP(compare));
}
};
@ -54,12 +53,11 @@ public:
SizedWordRegister hold;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<EeTimersUnit_Base>(this),
CEREAL_NVP(hold)
);
CEREAL_NVP(hold));
}
};

7
liborbum/src/Resources/Ee/Timers/REeTimers.hpp
View file

@ -21,14 +21,13 @@ public:
EeTimersUnit units[Constants::EE::Timers::NUMBER_TIMERS];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(unit_0),
CEREAL_NVP(unit_1),
CEREAL_NVP(unit_2),
CEREAL_NVP(unit_3)
);
CEREAL_NVP(unit_3));
}
};

7
liborbum/src/Resources/Ee/Vpu/RVpu.hpp
View file

@ -20,13 +20,12 @@ public:
RVu vu;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(stat),
CEREAL_NVP(vif),
CEREAL_NVP(vu)
);
CEREAL_NVP(vu));
}
};

7
liborbum/src/Resources/Ee/Vpu/Vif/RVif.hpp
View file

@ -16,12 +16,11 @@ public:
VifUnit_Base unit_1;
VifUnit_Base* units[Constants::EE::VPU::VIF::NUMBER_VIF_CORES];
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(unit_0),
CEREAL_NVP(unit_1)
);
CEREAL_NVP(unit_1));
}
};

7
liborbum/src/Resources/Ee/Vpu/Vif/VifUnits.hpp
View file

@ -43,8 +43,8 @@ public:
VifUnitRegister_Err err;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(r0),
@ -69,7 +69,6 @@ public:
CEREAL_NVP(code),
CEREAL_NVP(stat),
CEREAL_NVP(fbrst),
CEREAL_NVP(err)
);
CEREAL_NVP(err));
}
};

7
liborbum/src/Resources/Ee/Vpu/Vu/RVu.hpp
View file

@ -21,13 +21,12 @@ public:
VuRegister_Fbrst fbrst;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(unit_0),
CEREAL_NVP(unit_1),
CEREAL_NVP(fbrst)
);
CEREAL_NVP(fbrst));
}
};

13
liborbum/src/Resources/Ee/Vpu/Vu/VuBranchDelaySlot.hpp
View file

@ -9,10 +9,10 @@
/// BranchDelaySlot, modified slightly for the VUs.
/// See BranchDelaySlot for more documentation.
template <size_t slots = 1>
class VuBranchDelaySlot : public BranchDelaySlot<slots>
class VuBranchDelaySlot : public BranchDelaySlot<slots>
{
public:
VuBranchDelaySlot() :
VuBranchDelaySlot() :
second_branch_pc(0),
second_branch_pending(false),
BranchDelaySlot<slots>()
@ -98,16 +98,15 @@ private:
uptr second_branch_pc;
bool second_branch_pending;
// Serialization
// Serialization
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(current_slot),
CEREAL_NVP(branch_pc),
CEREAL_NVP(second_branch_pc),
CEREAL_NVP(second_branch_pending)
);
CEREAL_NVP(second_branch_pending));
}
};

7
liborbum/src/Resources/Ee/Vpu/Vu/VuInstruction.cpp
View file

@ -1,10 +1,11 @@
#include "Resources/Ee/Vpu/Vu/VuInstruction.hpp"
#include "Resources/Ee/Vpu/Vu/VuPipelines.hpp"
MipsInstructionInfo VU_INSTRUCTION_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTRUCTIONS] =
{
// Most VU instructions (Upper Instructions, Flags, Integer Store/Load...)
// follow the basic FMAC pipeline, which has 3 execution stages.
// Most VU instructions (Upper Instructions, Flags, Integer Store/Load...)
// follow the basic FMAC pipeline, which has 3 execution stages.
// Stalls on data hazard (when the same field of the same register is accessed
// by following instructions while the first instruction is still running).
@ -14,7 +15,7 @@ MipsInstructionInfo VU_INSTRUCTION_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTR
// unit at the same time). There is no data hazard - the original Q register
// (containing results from last FDIV operation) is used instead.
// Instructions prefixed with "E" follow EFU pipeline, which is similar to
// Instructions prefixed with "E" follow EFU pipeline, which is similar to
// FDIV pipeline, except that EFU is freed when it reaches the write-back
// stage, whereas FDIV is freed when the register is actually written.

4
liborbum/src/Resources/Ee/Vpu/Vu/VuInstruction.hpp
View file

@ -80,7 +80,6 @@ struct VuInstruction : public MipsInstruction
return fs();
}
ubyte opcode() const
{
return static_cast<ubyte>(OPCODE.extract_from(value));
@ -101,7 +100,8 @@ struct VuInstruction : public MipsInstruction
return static_cast<ubyte>(FSF.extract_from(value));
}
ubyte imm5() const {
ubyte imm5() const
{
// FD is IMM5 in some instructions
return static_cast<ubyte>(FD.extract_from(value));
}

342
liborbum/src/Resources/Ee/Vpu/Vu/VuInstructionDecoder.cpp
View file

@ -5,175 +5,175 @@
/// stores the destination reg, while index 1, 2 & 3 stores the source reg(s).
/// If the destination bitfield is set to nullopt, then it is assumed that the
/// instruction uses special registers such as P, Q or ACC.
VuDecodedInst VU_DECODE_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTRUCTIONS] {
VuDecodedInst VU_DECODE_TABLE[Constants::EE::VPU::VU::NUMBER_VU_INSTRUCTIONS]{
// DESTINATION SOURCE (1) SOURCE (2) SOURCE (3) FIELDS
// Upper Instructions
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ABS
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // ADD
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // ADDi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // ADDq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // ADDA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // ADDAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // ADDAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // SUB
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // SUBi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // SUBq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // SUBA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // SUBAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // SUBAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MUL
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MULi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // MULq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MULA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MULAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // MULAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_3
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MADD
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MADDi
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MADDq
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_0
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_1
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_2
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MADDA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MADDAi
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MADDAq
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_3
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MSUB
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MSUBi
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MSUBq
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_0
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_1
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_2
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MSUBA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MSUBAi
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MSUBAq
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MAX
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MAXi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MINI
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MINIi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // OPMULA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // OPMSUB
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // NOP
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI0
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI4
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI12
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI15
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF0
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF4
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF12
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF15
VuDecodedInst(VuSpecialRegs::CLIP, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // CLIP
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ABS
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // ADD
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // ADDi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // ADDq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // ADDA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // ADDAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // ADDAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // ADDAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // SUB
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // SUBi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // SUBq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // SUBA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // SUBAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // SUBAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // SUBAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MUL
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MULi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // MULq
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MULA
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MULAi
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, std::nullopt, VuDecodedInst::Dest), // MULAq
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MULAbc_3
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MADD
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MADDi
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MADDq
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_0
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_1
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_2
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MADDA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MADDAi
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MADDAq
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MADDAbc_3
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MSUB
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MSUBi
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MSUBq
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_0
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_1
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_2
VuDecodedInst(VuInstruction::FD, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // MSUBA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::I, VuDecodedInst::Dest), // MSUBAi
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuSpecialRegs::Q, VuDecodedInst::Dest), // MSUBAq
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_0
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_1
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_2
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Bc), // MSUBAbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MAX
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MAXi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MAXbc_3
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // MINI
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuSpecialRegs::I, std::nullopt, VuDecodedInst::Dest), // MINIi
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_0
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_1
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_2
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Bc), // MINIbc_3
VuDecodedInst(VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // OPMULA
VuDecodedInst(VuSpecialRegs::ACC, VuSpecialRegs::ACC, VuInstruction::FS, VuInstruction::FT, VuDecodedInst::Dest), // OPMSUB
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // NOP
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI0
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI4
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI12
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // FTOI15
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF0
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF4
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF12
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ITOF15
VuDecodedInst(VuSpecialRegs::CLIP, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Dest), // CLIP
// Lower Instructions
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::FsfFtf), // DIV
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // SQRT
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::FsfFtf), // RSQRT
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IADD
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IADDI
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IADDIU
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IAND
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IOR
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // ISUB
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISUBI
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MOVE
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MFIR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // MTIR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MR32
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQ
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQD
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQI
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQ
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQD
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQI
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ILW
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISW
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ILWR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISWR
VuDecodedInst(VuSpecialRegs::R, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // RINIT
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::R, std::nullopt, std::nullopt, VuDecodedInst::Dest), // RGET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::R, std::nullopt, std::nullopt, VuDecodedInst::Dest), // RNEXT
VuDecodedInst(VuSpecialRegs::R, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // RXOR
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // WAITQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FSAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FSEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FSOR
VuDecodedInst(VuSpecialRegs::SF, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FSSET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int ), // FMAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int ), // FMEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int ), // FMOR
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FCAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FCEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FCOR
VuDecodedInst(VuSpecialRegs::CLIP, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FCSET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int ), // FCGET
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FT, VuInstruction::FS, std::nullopt, VuDecodedInst::Int ), // IBEQ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int ), // IBGEZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int ), // IBGTZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int ), // IBLEZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int ), // IBLTZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FT, VuInstruction::FS, std::nullopt, VuDecodedInst::Int ), // IBNE
VuDecodedInst(VuSpecialRegs::PC, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // B
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // BAL
VuDecodedInst(VuSpecialRegs::PC, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // J
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int ), // JALR
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::P, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MFP
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // WAITP
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ESADD
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ERSADD
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ELENG
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ERLENG
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // EATANxy
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // EATANxz
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ESUM
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ERCPR
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ESQRT
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ERSQRT
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ESIN
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // EATAN
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // EEXP
VuDecodedInst(std::nullopt, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // XGKICK
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // XTOP
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // XITOP
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::FsfFtf), // DIV
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // SQRT
VuDecodedInst(VuSpecialRegs::Q, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::FsfFtf), // RSQRT
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IADD
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IADDI
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IADDIU
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IAND
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // IOR
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, VuInstruction::FT, std::nullopt, VuDecodedInst::Int), // ISUB
VuDecodedInst(VuInstruction::FD, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISUBI
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MOVE
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MFIR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // MTIR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MR32
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQ
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQD
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // LQI
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQ
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQD
VuDecodedInst(VuInstruction::FS, VuInstruction::FT, std::nullopt, std::nullopt, VuDecodedInst::Dest), // SQI
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ILW
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISW
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ILWR
VuDecodedInst(VuInstruction::FT, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // ISWR
VuDecodedInst(VuSpecialRegs::R, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // RINIT
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::R, std::nullopt, std::nullopt, VuDecodedInst::Dest), // RGET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::R, std::nullopt, std::nullopt, VuDecodedInst::Dest), // RNEXT
VuDecodedInst(VuSpecialRegs::R, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // RXOR
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // WAITQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int), // FSAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int), // FSEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::SF, std::nullopt, std::nullopt, VuDecodedInst::Int), // FSOR
VuDecodedInst(VuSpecialRegs::SF, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // FSSET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int), // FMAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int), // FMEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::MAC, VuInstruction::FS, std::nullopt, VuDecodedInst::Int), // FMOR
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int), // FCAND
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int), // FCEQ
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int), // FCOR
VuDecodedInst(VuSpecialRegs::CLIP, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // FCSET
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::CLIP, std::nullopt, std::nullopt, VuDecodedInst::Int), // FCGET
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FT, VuInstruction::FS, std::nullopt, VuDecodedInst::Int), // IBEQ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IBGEZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IBGTZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IBLEZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // IBLTZ
VuDecodedInst(VuSpecialRegs::PC, VuInstruction::FT, VuInstruction::FS, std::nullopt, VuDecodedInst::Int), // IBNE
VuDecodedInst(VuSpecialRegs::PC, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // B
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // BAL
VuDecodedInst(VuSpecialRegs::PC, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // J
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // JALR
VuDecodedInst(VuInstruction::FT, VuSpecialRegs::P, std::nullopt, std::nullopt, VuDecodedInst::Dest), // MFP
VuDecodedInst(std::nullopt, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Dest), // WAITP
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ESADD
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ERSADD
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ELENG
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ERLENG
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // EATANxy
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // EATANxz
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Dest), // ESUM
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ERCPR
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ESQRT
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ERSQRT
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // ESIN
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // EATAN
VuDecodedInst(VuSpecialRegs::P, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::FsfFtf), // EEXP
VuDecodedInst(std::nullopt, VuInstruction::FS, std::nullopt, std::nullopt, VuDecodedInst::Int), // XGKICK
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // XTOP
VuDecodedInst(VuInstruction::FT, std::nullopt, std::nullopt, std::nullopt, VuDecodedInst::Int), // XITOP
};
VuInstructionDecoder::VuInstructionDecoder(VuInstruction lower, VuInstruction upper) :
@ -220,11 +220,10 @@ std::optional<int> VuInstructionDecoder::upper_dest() const
std::optional<int> VuInstructionDecoder::upper_src(int index) const
{
const std::optional<VuDecodeInfo>* src_regs[3] = {
const std::optional<VuDecodeInfo>* src_regs[3] = {
&decoded_inst_upper.source_reg_1,
&decoded_inst_upper.source_reg_2,
&decoded_inst_upper.source_reg_3
};
&decoded_inst_upper.source_reg_3};
if (src_regs[index]->has_value())
{
@ -254,11 +253,10 @@ std::optional<int> VuInstructionDecoder::lower_dest() const
std::optional<int> VuInstructionDecoder::lower_src(int index) const
{
const std::optional<VuDecodeInfo>* src_regs[3] = {
const std::optional<VuDecodeInfo>* src_regs[3] = {
&decoded_inst_lower.source_reg_1,
&decoded_inst_lower.source_reg_2,
&decoded_inst_lower.source_reg_3
};
&decoded_inst_lower.source_reg_3};
if (src_regs[index]->has_value())
{

7
liborbum/src/Resources/Ee/Vpu/Vu/VuInstructionDecoder.hpp
View file

@ -6,7 +6,7 @@
#include "Common/Types/Bitfield.hpp"
#include "Resources/Ee/Vpu/Vu/VuInstruction.hpp"
enum class VuSpecialRegs
enum class VuSpecialRegs
{
ACC,
CLIP,
@ -48,8 +48,7 @@ struct VuDecodedInst
std::optional<VuDecodeInfo> src_1,
std::optional<VuDecodeInfo> src_2,
std::optional<VuDecodeInfo> src_3,
int dest_field
) :
int dest_field) :
dest_reg(dest),
source_reg_1(src_1),
source_reg_2(src_2),
@ -62,7 +61,7 @@ struct VuDecodedInst
std::optional<VuDecodeInfo> source_reg_1;
std::optional<VuDecodeInfo> source_reg_2;
std::optional<VuDecodeInfo> source_reg_3;
int field;
};

7
liborbum/src/Resources/Ee/Vpu/Vu/VuPipelines.hpp
View file

@ -5,7 +5,8 @@
struct VuPipeline
{
enum {
enum
{
FMAC = 0,
FDIV = 1,
EFU = 2,
@ -42,7 +43,7 @@ struct FmacPipeline : public MipsPipeline
{
const uhword using_reg = using_register >> 4;
const uhword reg_field = using_register & 0b1111;
// True if the pipeline is running, is using the same register, and is using the same fields
// Also true if it is VF00 that is being written into (it is hardwired to 0)
return is_running() && (using_reg == reg) && ((reg_field ^ field) != 0b1111);
@ -71,7 +72,7 @@ struct FdivPipeline : public MipsPipeline
struct EfuPipeline : public MipsPipeline
{
using MipsPipeline::MipsPipeline;
SizedWordRegister new_p;
};

2
liborbum/src/Resources/Ee/Vpu/Vu/VuRegisters.hpp
View file

@ -17,7 +17,7 @@ public:
static constexpr Bitfield TE1 = Bitfield(11, 1);
// Field extraction methods
ubyte fb(uword core_id)
{
// Small explanation: core_id << 3 = core_id * 8

2
liborbum/src/Resources/Ee/Vpu/Vu/VuState.hpp
View file

@ -1,6 +1,6 @@
#pragma once
enum class VuOperationState
enum class VuOperationState
{
Ready,
Run,

26
liborbum/src/Resources/Ee/Vpu/Vu/VuUnits.hpp
View file

@ -1,8 +1,9 @@
#pragma once
#include <optional>
#include <cereal/cereal.hpp>
#include <cereal/types/polymorphic.hpp>
#include <optional>
#include "Common/Constants.hpp"
#include "Common/Types/Bus/ByteBus.hpp"
@ -83,7 +84,7 @@ public:
/// VU operation state. The VU has 3 operation states: Ready, Run, Stop.
VuOperationState operation_state;
/// VU pipelines.
FmacPipeline fmac[4];
FdivPipeline fdiv;
@ -92,8 +93,8 @@ public:
LsuPipeline lsu;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(vf),
@ -107,8 +108,7 @@ public:
CEREAL_NVP(mac),
CEREAL_NVP(clipping),
CEREAL_NVP(pc),
CEREAL_NVP(cmsar)
);
CEREAL_NVP(cmsar));
}
};
@ -141,14 +141,13 @@ public:
std::optional<SizedWordRegister> transferred_reg;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<VuUnit_Base>(this),
CEREAL_NVP(memory_micro),
CEREAL_NVP(memory_mem)
);
CEREAL_NVP(memory_mem));
}
};
@ -163,13 +162,12 @@ public:
ArrayByteMemory memory_mem; // 16 KiB.
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<VuUnit_Base>(this),
CEREAL_NVP(memory_micro),
CEREAL_NVP(memory_mem)
);
CEREAL_NVP(memory_mem));
}
};

4
liborbum/src/Resources/Gs/Crtc/RCrtc.hpp
View file

@ -4,8 +4,8 @@
class RCrtc
{
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
}
};

7
liborbum/src/Resources/Gs/RGs.hpp
View file

@ -48,8 +48,8 @@ public:
ArrayByteMemory memory_2000;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(crtc),
@ -77,7 +77,6 @@ public:
CEREAL_NVP(siglblid),
CEREAL_NVP(memory_1090),
CEREAL_NVP(memory_1100),
CEREAL_NVP(memory_2000)
);
CEREAL_NVP(memory_2000));
}
};

7
liborbum/src/Resources/Iop/Core/IopCoreCop0.hpp
View file

@ -45,8 +45,8 @@ public:
SizedWordRegister* registers[Constants::IOP::IOPCore::COP0::NUMBER_REGISTERS];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(indx),
@ -65,7 +65,6 @@ public:
CEREAL_NVP(cause),
CEREAL_NVP(epc),
CEREAL_NVP(prid),
CEREAL_NVP(erreg)
);
CEREAL_NVP(erreg));
}
};

14
liborbum/src/Resources/Iop/Core/IopCoreCop0Registers.hpp
View file

@ -72,14 +72,13 @@ private:
void handle_operating_context_update();
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(interrupts_masked),
CEREAL_NVP(operating_context)
);
CEREAL_NVP(operating_context));
}
};
@ -111,13 +110,12 @@ private:
bool irq_lines[8];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(irq_lines)
);
CEREAL_NVP(irq_lines));
}
};

7
liborbum/src/Resources/Iop/Core/IopCoreR3000.hpp
View file

@ -34,15 +34,14 @@ public:
SizedWordRegister lo;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pc),
CEREAL_NVP(bdelay),
CEREAL_NVP(gpr),
CEREAL_NVP(hi),
CEREAL_NVP(lo)
);
CEREAL_NVP(lo));
}
};

7
liborbum/src/Resources/Iop/Core/RIopCore.hpp
View file

@ -21,13 +21,12 @@ public:
ArrayByteMemory scratchpad_memory;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(r3000),
CEREAL_NVP(cop0),
CEREAL_NVP(scratchpad_memory)
);
CEREAL_NVP(scratchpad_memory));
}
};

14
liborbum/src/Resources/Iop/Dmac/IopDmacChannelRegisters.hpp
View file

@ -67,14 +67,13 @@ public:
IopDmatag dma_tag;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(dma_started),
CEREAL_NVP(dma_tag)
);
CEREAL_NVP(dma_tag));
}
};
@ -102,13 +101,12 @@ public:
size_t transfer_length;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(transfer_length)
);
CEREAL_NVP(transfer_length));
}
};

14
liborbum/src/Resources/Iop/Dmac/IopDmacChannels.hpp
View file

@ -46,14 +46,13 @@ public:
IopDmacChannelRegister_Bcr bcr;
IopDmacChannelRegister_Chcr_Ty chcr;
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(madr),
CEREAL_NVP(bcr),
CEREAL_NVP(chcr)
);
CEREAL_NVP(chcr));
}
};
@ -70,12 +69,11 @@ public:
SizedWordRegister tadr;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<IopDmacChannel_Base<IopDmacChannelRegister_Chcr_Ty>>(this),
CEREAL_NVP(tadr)
);
CEREAL_NVP(tadr));
}
};

7
liborbum/src/Resources/Iop/Dmac/IopDmatag.hpp
View file

@ -61,12 +61,11 @@ public:
uword tag1;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(tag0),
CEREAL_NVP(tag1)
);
CEREAL_NVP(tag1));
}
};

7
liborbum/src/Resources/Iop/Dmac/RIopDmac.hpp
View file

@ -45,8 +45,8 @@ public:
IopDmacChannel channels[Constants::IOP::DMAC::NUMBER_DMAC_CHANNELS - 1];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pcr0),
@ -66,7 +66,6 @@ public:
CEREAL_NVP(channel_sif0),
CEREAL_NVP(channel_sif1),
CEREAL_NVP(channel_tosio2),
CEREAL_NVP(channel_fromsio2)
);
CEREAL_NVP(channel_fromsio2));
}
};

7
liborbum/src/Resources/Iop/Intc/RIopIntc.hpp
View file

@ -13,13 +13,12 @@ public:
IopIntcRegister_Stat stat;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ctrl),
CEREAL_NVP(mask),
CEREAL_NVP(stat)
);
CEREAL_NVP(stat));
}
};

7
liborbum/src/Resources/Iop/RIop.hpp
View file

@ -71,8 +71,8 @@ public:
SizedWordRegister register_3800;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(core),
@ -109,7 +109,6 @@ public:
CEREAL_NVP(register_1568),
CEREAL_NVP(register_15f0),
CEREAL_NVP(register_2070),
CEREAL_NVP(register_3800)
);
CEREAL_NVP(register_3800));
}
};

7
liborbum/src/Resources/Iop/Sio0/RSio0.hpp
View file

@ -16,14 +16,13 @@ public:
Sio0Register_Ctrl ctrl;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(data),
CEREAL_NVP(stat),
CEREAL_NVP(mode),
CEREAL_NVP(ctrl)
);
CEREAL_NVP(ctrl));
}
};

7
liborbum/src/Resources/Iop/Sio0/Sio0Registers.hpp
View file

@ -71,12 +71,11 @@ public:
Sio0Register_Stat* stat;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(command_queue),
CEREAL_NVP(response_queue)
);
CEREAL_NVP(response_queue));
}
};

7
liborbum/src/Resources/Iop/Sio2/RSio2.hpp
View file

@ -46,8 +46,8 @@ public:
SizedWordRegister intr; // Also known as the STAT register.
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(port_0),
@ -72,7 +72,6 @@ public:
CEREAL_NVP(recv3),
CEREAL_NVP(register_8278),
CEREAL_NVP(register_827c),
CEREAL_NVP(intr)
);
CEREAL_NVP(intr));
}
};

7
liborbum/src/Resources/Iop/Sio2/Sio2PortRegisters.hpp
View file

@ -40,13 +40,12 @@ public:
void byte_bus_write_uword(const BusContext context, const usize offset, const uword value) override;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(write_latch),
CEREAL_NVP(port_transfer_started)
);
CEREAL_NVP(port_transfer_started));
}
};

16
liborbum/src/Resources/Iop/Sio2/Sio2Ports.hpp
View file

@ -23,14 +23,13 @@ public:
Sio2PortRegister_Ctrl2 ctrl_2;
Sio2PortRegister_Ctrl3 ctrl_3;
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ctrl_1),
CEREAL_NVP(ctrl_2),
CEREAL_NVP(ctrl_3)
);
CEREAL_NVP(ctrl_3));
}
};
@ -39,12 +38,11 @@ class Sio2Port_Slim
{
public:
Sio2PortRegister_Ctrl3 ctrl_3;
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ctrl_3)
);
CEREAL_NVP(ctrl_3));
}
};

7
liborbum/src/Resources/Iop/Sio2/Sio2Registers.hpp
View file

@ -46,8 +46,8 @@ public:
bool write_latch;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
@ -55,7 +55,6 @@ public:
CEREAL_NVP(transfer_port),
CEREAL_NVP(transfer_port_count),
CEREAL_NVP(transfer_direction),
CEREAL_NVP(write_latch)
);
CEREAL_NVP(write_latch));
}
};

14
liborbum/src/Resources/Iop/Timers/IopTimersUnitRegisters.hpp
View file

@ -48,15 +48,14 @@ private:
int prescale_count;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(is_overflowed),
CEREAL_NVP(prescale_target),
CEREAL_NVP(prescale_count)
);
CEREAL_NVP(prescale_count));
}
};
@ -103,12 +102,11 @@ public:
std::pair<uword, ControllerEventType> get_properties(const int unit_id);
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedWordRegister>(this),
CEREAL_NVP(write_latch)
);
CEREAL_NVP(write_latch));
}
};

7
liborbum/src/Resources/Iop/Timers/IopTimersUnits.hpp
View file

@ -19,13 +19,12 @@ public:
SizedWordRegister compare;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(count),
CEREAL_NVP(mode),
CEREAL_NVP(compare)
);
CEREAL_NVP(compare));
}
};

7
liborbum/src/Resources/Iop/Timers/RIopTimers.hpp
View file

@ -23,8 +23,8 @@ public:
IopTimersUnit_Base* units[Constants::IOP::Timers::NUMBER_TIMERS];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(unit_0),
@ -32,7 +32,6 @@ public:
CEREAL_NVP(unit_2),
CEREAL_NVP(unit_3),
CEREAL_NVP(unit_4),
CEREAL_NVP(unit_5)
);
CEREAL_NVP(unit_5));
}
};

11
liborbum/src/Resources/RResources.hpp
View file

@ -75,14 +75,14 @@ public:
DmaFifoQueue<> fifo_tosio2;
public:
template<class Archive>
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(ee),
CEREAL_NVP(gs),
CEREAL_NVP(iop),
CEREAL_NVP(spu2),
CEREAL_NVP(gs),
CEREAL_NVP(iop),
CEREAL_NVP(spu2),
CEREAL_NVP(cdvd),
CEREAL_NVP(boot_rom),
CEREAL_NVP(rom1),
@ -114,8 +114,7 @@ public:
CEREAL_NVP(fifo_spu2c1),
CEREAL_NVP(fifo_dev9),
CEREAL_NVP(fifo_fromsio2),
CEREAL_NVP(fifo_tosio2)
);
CEREAL_NVP(fifo_tosio2));
}
};

7
liborbum/src/Resources/Spu2/RSpu2.hpp
View file

@ -45,8 +45,8 @@ public:
ArrayByteMemory memory_07ce;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(core_0),
@ -62,7 +62,6 @@ public:
CEREAL_NVP(memory_0346),
CEREAL_NVP(memory_0746),
CEREAL_NVP(memory_07b0),
CEREAL_NVP(memory_07ce)
);
CEREAL_NVP(memory_07ce));
}
};

7
liborbum/src/Resources/Spu2/Spu2CoreConstants.hpp
View file

@ -15,8 +15,7 @@ struct Spu2CoreConstants
};
static constexpr Spu2CoreInfo SPU2_STATIC_INFO[Constants::SPU2::NUMBER_CORES] =
{
{0x2000, 0x2200},
{0x2400, 0x2600}
};
{
{0x2000, 0x2200},
{0x2400, 0x2600}};
};

7
liborbum/src/Resources/Spu2/Spu2CoreRegisters.hpp
View file

@ -98,13 +98,12 @@ public:
size_t dma_offset;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
cereal::base_class<SizedHwordRegister>(this),
CEREAL_NVP(dma_offset)
);
CEREAL_NVP(dma_offset));
}
};

7
liborbum/src/Resources/Spu2/Spu2CoreVoice.hpp
View file

@ -25,8 +25,8 @@ public:
SizedHwordRegister naxl;
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(voll),
@ -42,7 +42,6 @@ public:
CEREAL_NVP(lsaxh),
CEREAL_NVP(lsaxl),
CEREAL_NVP(naxh),
CEREAL_NVP(naxl)
);
CEREAL_NVP(naxl));
}
};

7
liborbum/src/Resources/Spu2/Spu2Cores.hpp
View file

@ -148,8 +148,8 @@ public:
Spu2CoreVoice* voices[Constants::SPU2::NUMBER_CORE_VOICES];
public:
template<class Archive>
void serialize(Archive & archive)
template <class Archive>
void serialize(Archive& archive)
{
archive(
CEREAL_NVP(pmon0),
@ -271,7 +271,6 @@ public:
CEREAL_NVP(voice_20),
CEREAL_NVP(voice_21),
CEREAL_NVP(voice_22),
CEREAL_NVP(voice_23)
);
CEREAL_NVP(voice_23));
}
};

2
liborbum/src/Utilities/Utilities.hpp
View file

@ -31,7 +31,7 @@ int count_leading_bits(const sword value);
int count_trailing_zeros(const uword value);
/// Parses `source` of type U as a N-bit integer, converting it to an int of type T.
template<typename T, typename U, unsigned int N>
template <typename T, typename U, unsigned int N>
constexpr T extend_integer(const U source)
{
// For a 5 bit integer, it's the first 4 bits (0b01111)