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Author SHA1 Message Date
hch12907 8f9fe64e07 Core: adjust time slice and workers 
the change was accidentally included in 3b6cc1f7
 2019-01-26 15:03:06 +08:00
hch12907 3b6cc1f701 VPU: Split VPU0/1 into two threads 
- VU and VIF are no longer on separate threads
- Instead, they are now on the same "VPU" thread
- VPU is the one which is threaded now - VPU0/1 run on separate threads

This is done to (hopefully!) improve synchronization
 2019-01-26 00:43:21 +08:00
hch12907 65b1ae5dd2 VU: Have the VU base class take a reference to the VU memory 2018-12-24 01:20:23 +08:00
hch12907 cbb6054c96 VIF: add FBRST detection 2018-12-15 01:20:07 +08:00
hch12907 a64af809b3 VIF: Fix build 2018-12-14 18:24:03 +08:00
hch12907 62a7df628f VIF: Correctly calculate UNPACK subpacket length 2018-12-14 18:07:15 +08:00
hch12907 c15fd1fba1 VIF: Implement DIRECT* instructions 2018-11-24 21:52:15 +08:00
hch12907 bbf79d0a3a Utilities: Rename extend_integer to extend_integer_sign 2018-11-24 21:52:15 +08:00
hch12907 b3676c2232 VIF: Implement microprogram-related instructions 2018-11-24 21:52:15 +08:00
hch12907 7dc76e4c80 VIF: Split UNPACK instruction 2018-11-24 21:52:15 +08:00
hch12907 db74f7dd49 VIF: Implement SET instructions 2018-11-24 21:52:15 +08:00
hch12907 afcde2166d VIF: Basic implementation 2018-11-24 21:52:15 +08:00
hch12907 17bb55c132 EE/IOP/VU: Consistency 2018-11-24 21:52:15 +08:00
hch12907 8089b206dd GIF: Improve FIFO check 
fingers crossed that it fixes #1 again
 2018-11-24 21:48:55 +08:00
hch12907 620110cfa6 VU: Instruction decoder rework 2018-11-24 21:47:08 +08:00
Hoe Hao Cheng c9713cb365
Update README. 2018-11-06 21:00:38 +08:00
hch12907 dee67fb2b3 GIF: Attempt to fix #1 (FIFO soft-lock problem) 
instead of checking if there's an active path, check if the FIFO still contain data
 2018-11-06 17:20:29 +08:00
hch12907 c88d415692 common: Make register reading const 
- except ByteRegister, because SIO uses them weirdly
- source registers are now read-only
- hopefully, just hopefully, that the COP0s won't decide to screw up (read_uword() causes side effects)
if something weird happens I am definitely reverting this commit
 2018-11-05 15:31:58 +08:00
Hoe Hao Cheng eab850b050 Add a CONTRIBUTING.md 
- added this to fulfill GitHub's community guidelines, because ocd.
 2018-11-05 12:58:14 +08:00
hch12907 78082d2ce3 GIF: Finishing touches 2018-11-05 00:34:20 +08:00
hch12907 2e96c7db8b GIF: Add PATH3 intermittent mode support 2018-11-04 19:47:14 +08:00
hch12907 e1550da391 VIF: Split CVif into several files 
- MP is for microprogram-related instructions
- SET is for register-setting-related instructions
- TRANSFER and UNPACK are... well, for Transfer and unpack-related instructions
 2018-11-04 17:13:40 +08:00
hch12907 e686f6c3cd GIF: Fix EOP behaviour 2018-11-04 16:44:47 +08:00
hch12907 2eb2f4f86d Update README and add a LICENSE file 
it has been bugging me for too long
 2018-11-03 14:46:28 +08:00
hch12907 7e4ca5d4aa Made BranchDelaySlot slightly more readable... 2018-10-21 15:20:13 +08:00
hch12907 33ee436db0 GIF: Actually use the register classes and bugfixes 
other fixes:
- fixed GIF control flow
- improved GIF error messages (includes transfer mode now)
- Fix bitfield alignment detection
 2018-10-21 15:12:07 +08:00
hch12907 1452185156 Unified file encoding to utf8 
- some files were using utf8-bom
 2018-10-21 00:34:04 +08:00
hch12907 4e62239a94 Fix clang-7 and MSVC build 
- added missing includes
- fixed ambiguous Bitfield extract_from
- VU branch delay slot cleanup
- removed unused CGif function
- removed reference to removed variables
 2018-10-21 00:12:14 +08:00
hch12907 313f59a019 Try branch in branch delay slot support... 2018-10-18 19:50:24 +08:00
hch12907 dabf082d2f GIF: Add missing register GIF_CNT 2018-10-13 21:56:26 +08:00
hch12907 62bb9925ab Merge marco9999/gif-impl. 2018-10-12 18:44:34 +08:00
Hoe Hao Cheng cc9fd11233 Run clang-format and update README 2018-10-10 22:39:55 +08:00
hch12907 3492c0b152 Implement M-bit handling 
- only VU side, EE/COP2 side not implemented yet (another PR for that)
- this is a rough implementation, it doesnt even differentiate CPR and CCR
- also, a quick bugfix for WAITQ data hazard
 2018-10-10 22:35:14 +08:00
hch12907 ee45eefca9 fix MSVC build 2018-10-10 22:35:14 +08:00
hch12907 52e6bf9d99 Implement data hazard, register writing priority, proper CPI for VU interpreter 
- implemented data hazard
- implemented register writing priority
- proper CPI
- note: WAITP and WAITQ is handled as a data hazard (special case)
 2018-10-10 22:36:42 +08:00
hch12907 56b5e45d84 Implement VU pipelines 
note: this commit can be reverted if pipeline emulation is found to be unneccessary
- added MipsPipeline
- implemented VU pipelines for the interpreter
 2018-10-10 22:35:14 +08:00
hch12907 1d1212e57e Implement VU interpreter 2018-09-24 00:43:06 +08:00
Marco Satti 5286c1ad7a
Merge pull request #17 from hch12907/master 
VU bugfixes
 2018-09-23 22:42:33 +08:00
Marco Satti f83bf61314
Merge pull request #15 from hch12907/vu-interpreter 
VU instruction table
 2018-09-23 22:29:52 +08:00
hch12907 6483bdb285 Add CPI to the VU instructions 2018-09-20 23:24:37 +08:00
hch12907 e4339b22cc Fix VU integer load/store 
note that in ILW/ILWR, the operation is undefined if multiple fields are specified
 2018-09-18 23:11:08 +08:00
Marco Satti e10163634d Implement reglist and image mode of GIF. 2018-09-16 14:16:14 +08:00
Marco Satti 48c4efcce6 Implement gif packed mode 2018-09-09 19:15:22 +08:00
hch12907 16b3570c4b Fix missing MAC flag clears 2018-09-08 17:09:42 +08:00
Marco Satti 30ad98be49 Merge branch 'master' into gif-impl 2018-09-08 14:51:34 +08:00
hch12907 2e9293c49e Add VU instruction lookup table 
- also improved log message for IOP/EE Core instruction lookup
 2018-09-02 22:20:44 +08:00
Marco Satti c9c5e21b16
Merge pull request #14 from hch12907/master 
A great hunt for those pesky unimplemented VU instructions
 2018-09-02 21:46:27 +08:00
hch12907 f4abbb78f9 Add branch delay slots to VUs and squash some bugs 
- added branch delay slots to the VUs (todo: different ANDs for VU0 and VU1, VU0 has smaller micromem)
- fixed imm15 (forgot to lshift DEST by 11 bits)
- removed various warnings (heck, even fixed one bug!)
- extended the visibility of the members in BranchDelaySlot to protected
- [experimental] branching in branch delay slots
 2018-09-01 18:49:51 +08:00
hch12907 cabefebec9 Implement VU transfer instructions 
finally finished implementing those instructions!
also added some basic comments
 2018-08-26 01:55:24 +08:00
hch12907 9ead3c7cba Implement VU_OTHER instructions 2018-08-26 01:55:23 +08:00